Abstract: An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.

Abstract: In various examples, a trajectory prediction model provides interpretable trajectory predictions for autonomous and semi-autonomous systems and applications via counterfactual game-theoretic reasoning. Model-based latent variables can be formulated through responsibility evaluations. Responsibility can be broken into multiple components, such as safety and courtesy. Responsibility can be quantified, for example, by answering a counterfactual question: could an agent have executed differently to respect other agents' safety and be more courteous to others' plans? The framework can be used to abstract computed responsibility sequences into different responsibility levels and ground latent levels into a trajectory prediction model able to render interpretable and accurate inferences about trajectory.

Abstract: A base is configured for a bracket. The base includes a hollow body, a plurality of supporting branches, and an illuminating module. The hollow body is connected to the bracket and has a bottom part and a first sidewall. The bottom part has an open hole. The first sidewall has a transparent structure. The plurality of supporting branches is disposed around the hollow body to lift the hollow body. The illuminating module is disposed in the hollow body and includes a sleeve and a base plate. The sleeve has a second sidewall, a first end, and a second end opposite to the first end. The second sidewall has an opening. The position of the opening is corresponding to the transparent structure. The base plate is disposed on the first end. The base plate is provided with a light source. The light source projects light beams toward the second end.

Abstract: A display apparatus adapted for connecting with a supporting stand is provided. The supporting stand includes a clamping portion. The display apparatus includes a main body. The main body includes a back surface. The back surface includes a connecting hole. A fixing component is in the connecting hole. The clamping portion is adapted to reach into the connecting hole. When the clamping portion reaches into the connecting hole, the clamping portion is arranged around and abuts against the fixing component, so that the display apparatus is connected to the supporting stand.

Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second doped region, a third doped region, a second well, a fourth doped region, and a fifth doped region is provided. The substrate has a first conductivity type. The first well is disposed in the substrate and has a second conductivity type. The first doped region is disposed in the first well and has the second conductivity type. The second doped region is disposed in the first well and has the first conductivity type. The third doped region is disposed in the first well and has the first conductivity type. The second well is disposed in the first well. The fourth doped region is disposed in the second well and has the first conductivity type. The fifth doped region is disposed in the second well and has the second conductivity type.

Abstract: A driving circuit includes a detection circuit, a control circuit, and a power device. The detection circuit is coupled between first and second power terminals. The detection circuit generates a detection voltage at a detection node based on a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor device with a back-to-back connection structure that is coupled between a bonding pad and a first node and controlled by the detection voltage to generate a driving voltage at the first node for controlling the power device. In response to an electrostatic discharge event occurring on the bonding pad, the transistor device is turned on according to the detection voltage, and the power device is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power terminal.

Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Abstract: A base is configured for a bracket. The base includes a hollow body, a plurality of supporting branches, and an illuminating module. The hollow body is connected to the bracket and has a bottom part and a first sidewall. The bottom part has an open hole. The first sidewall has a transparent structure. The plurality of supporting branches is disposed around the hollow body to lift the hollow body. The illuminating module is disposed in the hollow body and includes a sleeve and a base plate. The sleeve has a second sidewall, a first end, and a second end opposite to the first end. The second sidewall has an opening. The position of the opening is corresponding to the transparent structure. The base plate is disposed on the first end. The base plate is provided with a light source. The light source projects light beams toward the second end.

Abstract: An ESD protection circuit includes a buffer circuit, a driving circuit, and a power-clamping circuit. The buffer circuit includes first and second transistors having a first conductivity type coupled in a cascade configuration between a first node and a first power supply node. A bonding pad is coupled to the first node. The drive circuit determines a state of at least one of the first and second transistors according to a control voltage. The drive circuit includes a third transistor having a second conductivity type, which is coupled between a second power supply node and a gate of the first transistor and is controlled by the control signal. The power-clamping circuit is coupled to the bonding pad and a gate of the third transistor at a second node. The control voltage is generated at the second node and determined by a voltage at the bonding pad.

Abstract: A display apparatus adapted for connecting with a supporting stand is provided. The supporting stand includes a clamping portion. The display apparatus includes a main body. The main body includes a back surface. The back surface includes a connecting hole. A fixing component is in the connecting hole. The clamping portion is adapted to reach into the connecting hole. When the clamping portion reaches into the connecting hole, the clamping portion is arranged around and abuts against the fixing component, so that the display apparatus is connected to the supporting stand.

Abstract: A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Abstract: A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

Abstract: An operating circuit is provided. A first N-type transistor determines whether to create an open circuit between a core circuit and a ground terminal according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific node according to the first detection signal.

Abstract: An electronic device and a display thereof are provided. The electronic device includes a display and a supporting device. The display includes a display panel, a back cover, and a connecting member. The back cover is disposed on the display panel, and includes an inner surface, an outer surface opposite to the inner surface, and a mounting hole penetrating the inner surface and the outer surface. The inner surface faces the display panel. The mounting hole is disposed on a central region of the back cover. The connecting member is disposed on the inner surface at a position corresponding to the mounting hole, and includes a screw hole. The supporting device includes a detachable fixer connected to the screw hole. Thus, it is convenient for a user to connect the display to different supporting devices.

Abstract: A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.

Abstract: An operating circuit is provided. A first N-type transistor determines whether to turn the path between a core circuit and a ground terminal on or off according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific circuit according to the first detection signal.

Abstract: An electronic device and a display thereof are provided. The electronic device includes a display and a supporting device. The display includes a display panel, a back cover, and a connecting member. The back cover is disposed on the display panel, and includes an inner surface, an outer surface opposite to the inner surface, and a mounting hole penetrating the inner surface and the outer surface. The inner surface faces the display panel. The mounting hole is disposed on a central region of the back cover. The connecting member is disposed on the inner surface at a position corresponding to the mounting hole, and includes a screw hole. The supporting device includes a detachable fixer connected to the screw hole. Thus, it is convenient for a user to connect the display to different supporting devices.