Abstract: A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.

Abstract: A method for treating a semiconductor structure comprising memory devices is provided, wherein a forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

Abstract: A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.

Abstract: A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

Abstract: A method for treating a semiconductor structure is provided. A semiconductor structure comprising memory devices is provided. A forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

Abstract: A ReRAM device is provided. The ReRAM device comprises a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer, and a ReRAM unit disposed on the first conductive connecting structure. The first dielectric layer comprises a first insulating layer disposed on the substrate, and a stop layer disposed on the first insulating layer and contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer.

Abstract: A method for physically unclonable function-identification (PUF-ID) generation includes: providing a PUF array having programmable resistance memory cells; performing a forming procedure followed by a programming procedure on all of the programmable resistance memory cells of the PUF array; performing an estimation process to estimate randomness of the PUF array, by comparing a reference current of a base unit to a total current passing through all of the programmable resistance memory cells for obtaining a PUF randomness; determining a setting result of randomness based on the estimation process; and generating a PUF-ID according to the setting result of randomness.

Abstract: A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.

Abstract: A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.

Abstract: A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and a low resistance state (LRS); a reference array including a plurality of reference cells, the memory cells and the reference cells having the same impedance-temperature relationship, the reference cells being in a middle resistance state between HRS and LRS; an average circuit configured for averaging respective reference currents from the reference cells of the reference array into an average reference current; and a comparator configured for comparing a plurality of respective memory currents from the memory cells of the memory array with the average reference current to obtain a plurality of output data of the memory cells of the memory array and to determine respective impedance states of the memory cells of the memory array.

Abstract: A method for operating a resistance switching memory device is provided, wherein the method includes a first program process, and the first program process includes steps as follows: A programming pulse having a first polarity is firstly applied to at least one resistance switching memory cell of the NVM device. A first verifying pulse with a verifying voltage is then applied to the resistance switching memory cell. A first settling pulse is applied to the resistance switching memory cell prior to or after the verifying pulse is applied, wherein the first settling pulse includes a settling voltage having a second polarity opposite to the first polarity and an absolute value substantially less than that of the verifying voltage.

Abstract: A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.

Abstract: A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.

Abstract: A device matching verification method is provided. The device matching verification method includes reading, respectively, first color code information stored in a cradle device and second color code information stored in a memory device of an electronic device; transforming the first color code information to display a first color code on a first display region of a display device of the electronic device; transforming the second color code information to display a second color code on a second display region of the display device; and determining whether the cradle device matches the electronic device or not according to the first color code and the second color code.

Abstract: A computer apparatus and a resetting method for a real time clock (RTC) of the computer apparatus are provided. The resetting method for the RTC includes: generating a judging result by determining whether the computer apparatus is in an S5 state and determining whether a plurality of pre-determined keys are simultaneously pressed; pulling down a resume reset signal according to the judging result and correspondingly pulling down an operating voltage; pulling down an S5 enabling signal after pulling down the operating voltage for a pre-determined delay time; generating an RTC reset signal for resetting the RTC after pulling down the S5 enabling signal is pulled down.

Abstract: A computer apparatus and a resetting method for a real time clock (RTC) of the computer apparatus are provided. The resetting method for the RTC includes: generating a judging result by determining whether the computer apparatus is in an S5 state and determining whether a plurality of pre-determined keys are simultaneously pressed; pulling down a resume reset signal according to the judging result and correspondingly pulling down an operating voltage; pulling down an S5 enabling signal after pulling down the operating voltage for a pre-determined delay time; generating an RTC reset signal for resetting the RTC after pulling down the S5 enabling signal is pulled down.