Abstract: Various embodiments provide for multi-threaded network routing of a circuit design based on partitioning networks of the circuit design, which can enable partitioning routing tasks for the circuit design. More particularly, some embodiments iteratively partition networks of a circuit design into groups of networks, which enable various embodiments to schedule routing tasks for those groups of networks to available threads such that no two networks of the circuit design with overlapping routing regions are routed at the same time, and such that idle time of each thread (e.g., time where thread has no work or is waiting for another thread to finish) can be minimized.

Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Abstract: A soft-start control circuit is provided. The soft-start control circuit includes a load switch, a driving unit and a filtering unit. The first terminal of the load switch is configured to receive an input voltage. The control terminal of the load switch is configured to receive a switching signal and perform switching between on and off according to the switching signal, thereby performing a soft-start operation. The second terminal of the load switch is configured to provide a switched voltage. The driving unit is configured to provide a switching signal according to a control signal and release a parasitic charge stored in the load switch when the load switch is turned off. The filtering unit is configured to convert the switched voltage into an output voltage.

Abstract: Various embodiments described herein provide for routing of wires of a network of a circuit design based on pin placement within a routing blockage. In particular, various embodiments provide a routing solution for a circuit design with zero blockage violation when there is no pin inside routing blockage of the circuit design, and uses a parameter (e.g., an adjustable parameter) that controls accuracy at which a routing process handles a pin (e.g., as placed by a placement stage) in routing blockage of the circuit design. For example, the parameter can control how much detour is acceptable when handling routing for a pin inside a routing blockage.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.

Abstract: Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.

Abstract: A soft-start control circuit is provided. The soft-start control circuit includes a load switch, a driving unit and a filtering unit. The first terminal of the load switch is configured to receive an input voltage. The control terminal of the load switch is configured to receive a switching signal and perform switching between on and off according to the switching signal, thereby performing a soft-start operation. The second terminal of the load switch is configured to provide a switched voltage. The driving unit is configured to provide a switching signal according to a control signal and release a parasitic charge stored in the load switch when the load switch is turned off. The filtering unit is configured to convert the switched voltage into an output voltage.

Abstract: A soft-start control circuit is provided. The soft-start control circuit includes a load switch, a driving unit and a filtering unit. The first terminal of the load switch is configured to receive an input voltage. The control terminal of the load switch is configured to receive a switching signal and perform switching between on and off according to the switching signal, thereby performing a soft-start operation. The second terminal of the load switch is configured to provide a switched voltage. The driving unit is configured to provide a switching signal according to a control signal and release a parasitic charge stored in the load switch when the load switch is turned off. The filtering unit is configured to convert the switched voltage into an output voltage.

Abstract: A multi-chip MIMO radar system includes a plurality of transmitters and a plurality of receivers. Each of the pluralities of transmitters and receivers are arranged across a plurality of chips. The multi-chip MIMO radar system is configured to provide an exemplary chip synchronization such that the transmitters and receivers of each chip of the radar system are synchronized with the transmitters and receivers of every other chip of the radar system.

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.

Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

Abstract: A power converter module includes a carrier board, a transformer, and an inductor. A converter and a rectifying unit are arranged on the carrier board. The transformer includes a primary winding portion and a secondary winding portion. The primary winding portion is arranged on first side of the carrier board and coupled to an output terminal of the converter. The secondary winding portion is arranged between the first side and the primary winding portion and coupled to the rectifying unit. The inductor includes an input portion and an output portion. The input portion is arranged on the first side and coupled to the rectifying unit. The secondary winding portion is implemented with a conductive plate, and the input portion and the conductive plate are integrally formed. The output portion is coupled to the input portion and arranged on the first side or a second side of the carrier board.

Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.

Abstract: A power converter module includes a carrier board, a transformer, and an inductor. A converter and a rectifying unit are arranged on the carrier board. The transformer includes a primary winding portion and a secondary winding portion. The primary winding portion is arranged on first side of the carrier board and coupled to an output terminal of the converter. The secondary winding portion is arranged between the first side and the primary winding portion and coupled to the rectifying unit. The inductor includes an input portion and an output portion. The input portion is arranged on the first side and coupled to the rectifying unit. The secondary winding portion is implemented with a conductive plate, and the input portion and the conductive plate are integrally formed. The output portion is coupled to the input portion and arranged on the first side or a second side of the carrier board.

Abstract: A scalable system that can secure, mount, and store a plurality of beverages of different sizes, shapes, and capacities on mobile racks for performing processor-assisted, ‘hands-free’ ingredient dispensing and other ancillary dispensing activities. The mobile racks can be individually extracted from the system to perform empty beverage replacement. A beverage plug and tap is inserted into an opening of a beverage and the beverage plug compressed to seal the beverage opening. A spout is attached to the tap and fastened. The beverage is mounted onto a cradle in a dispensing position, the spout is inserted into a spout controller, and the mobile rack stowed back to the system with the mounted beverage ready for ingredient dispensing. A client-server applies the methods of a messaging protocol to manage the distributions of messaging protocol packets between connected clients over a wireless network.

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.