Patents by Inventor Kai Chow

Kai Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200292666
    Abstract: A multi-chip MIMO radar system includes a plurality of transmitters and a plurality of receivers. Each of the pluralities of transmitters and receivers are arranged across a plurality of chips. The multi-chip MIMO radar system is configured to provide an exemplary chip synchronization such that the transmitters and receivers of each chip of the radar system are synchronized with the transmitters and receivers of every other chip of the radar system.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Inventors: Monier Maher, Marius Goldenberg, Chung-Kai Chow, Frederick Rush, Otto A. Schmid
  • Patent number: 10755024
    Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 25, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing Kai Chow, Mehmet Yildiz, Zhuo Li
  • Patent number: 10685164
    Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 16, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li
  • Publication number: 20200161351
    Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 21, 2020
    Inventors: Hua Hong TAN, Chee Kay CHOW, Thian Hwee TAN, Wedanni Linsangan MICLA, Enrique Jr SARILE, Mario Arwin FABIAN, Dennis TRESNADO, Antonino II MILANES, Ming Koon ANG, Kian Soo LIM, Mauro Jr. DIONISIO, Teddy Joaquin CARREON
  • Patent number: 10566369
    Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 18, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Tim Thian Hwee Tan, Boon Pek Liew, Chee Kay Chow, Teddy Joaquin Carreon
  • Patent number: 10460063
    Abstract: Aspects of the present disclosure address improved systems and methods for routing based on enhanced routing topologies. Consistent with some embodiments, the method may include accessing a routing topology of an integrated circuit design and determining that a routing path of a net in the routing topology violates a routing constraint. In response to determining that the routing path violates the routing constraint, a routing guide is created to reroute the routing path. The routing path in the net is then rerouted using the routing guide, thereby producing an enhanced routing topology that reduces issues in detailed routing caused by the routing constraint violation.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10460065
    Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li, Charles Jay Alpert
  • Patent number: 10460066
    Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gracieli Posser, Wen-Hao Liu, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10355608
    Abstract: A power converter module includes a carrier board, a transformer, and an inductor. A converter and a rectifying unit are arranged on the carrier board. The transformer includes a primary winding portion and a secondary winding portion. The primary winding portion is arranged on first side of the carrier board and coupled to an output terminal of the converter. The secondary winding portion is arranged between the first side and the primary winding portion and coupled to the rectifying unit. The inductor includes an input portion and an output portion. The input portion is arranged on the first side and coupled to the rectifying unit. The secondary winding portion is implemented with a conductive plate, and the input portion and the conductive plate are integrally formed. The output portion is coupled to the input portion and arranged on the first side or a second side of the carrier board.
    Type: Grant
    Filed: December 10, 2017
    Date of Patent: July 16, 2019
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Wing-Kai Chow, Li-Yung Fu, Chung-Hang Lai
  • Patent number: 10289792
    Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Wen-Hao Liu, Gracieli Posser, Mehmet Can Yildiz
  • Publication number: 20190089259
    Abstract: A power converter module includes a carrier board, a transformer, and an inductor. A converter and a rectifying unit are arranged on the carrier board. The transformer includes a primary winding portion and a secondary winding portion. The primary winding portion is arranged on first side of the carrier board and coupled to an output terminal of the converter. The secondary winding portion is arranged between the first side and the primary winding portion and coupled to the rectifying unit. The inductor includes an input portion and an output portion. The input portion is arranged on the first side and coupled to the rectifying unit. The secondary winding portion is implemented with a conductive plate, and the input portion and the conductive plate are integrally formed. The output portion is coupled to the input portion and arranged on the first side or a second side of the carrier board.
    Type: Application
    Filed: December 10, 2017
    Publication date: March 21, 2019
    Inventors: Wing-Kai CHOW, Li-Yung FU, Chung-Hang LAI
  • Publication number: 20180186618
    Abstract: A scalable system that can secure, mount, and store a plurality of beverages of different sizes, shapes, and capacities on mobile racks for performing processor-assisted, ‘hands-free’ ingredient dispensing and other ancillary dispensing activities. The mobile racks can be individually extracted from the system to perform empty beverage replacement. A beverage plug and tap is inserted into an opening of a beverage and the beverage plug compressed to seal the beverage opening. A spout is attached to the tap and fastened. The beverage is mounted onto a cradle in a dispensing position, the spout is inserted into a spout controller, and the mobile rack stowed back to the system with the mounted beverage ready for ingredient dispensing. A client-server applies the methods of a messaging protocol to manage the distributions of messaging protocol packets between connected clients over a wireless network.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventor: kai chow
  • Publication number: 20180182801
    Abstract: A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 28, 2018
    Inventors: Tim Thian Hwee TAN, Boon Pek LIEW, Chee Kay CHOW, Teddy Joaquin CARREON
  • Patent number: 9785738
    Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 10, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Charles Jay Alpert, Zhuo Li, Wing Kai Chow, Wen-Hao Liu, Derong Liu
  • Patent number: 9705415
    Abstract: A power supply apparatus includes a power supply circuit and an active clamping circuit. The power supply circuit includes a secondary side rectifying unit and a voltage output side. The active clamping circuit includes a clamping energy-storing unit, a feedback control unit and a synchronous buck converter. The clamping energy-storing unit clamps and stores a voltage spike to obtain an energy-storing voltage. The feedback control unit detects the energy-storing voltage and informs the synchronous buck converter of the energy-storing voltage. The synchronous buck converter receives the energy-storing voltage and adjusts the energy-storing voltage to obtain an adjusted voltage when the energy-storing voltage is greater than a predetermined voltage. The synchronous buck converter sends the adjusted voltage to the voltage output side.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: July 11, 2017
    Assignee: Chicony Power Technology Co., Ltd.
    Inventors: Man-Chuen Wong, Wing-Kai Chow
  • Patent number: 9609271
    Abstract: Systems and methods provide location of an object via video conferencing. The systems and methods may be useful for applications that require remote assistance from an individual to help another individual locate an object or a feature within an image displayed on screen. The user of a local device may view the remote image for context of the environment. In some embodiments, the local user may help direct the remote user by directions to zoom in or out of the displayed image and may provide a frame to guide the remote user. A position in the remote image shown in the remote device is activated and displayed by the local user as an icon to help pinpoint the object location for the remote user.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: March 28, 2017
    Inventor: Ching-Kay Chow
  • Publication number: 20170025968
    Abstract: A power supply apparatus includes a power supply circuit and an active clamping circuit. The power supply circuit includes a secondary side rectifying unit and a voltage output side. The active clamping circuit includes a clamping energy-storing unit, a feedback control unit and a synchronous buck converter. The clamping energy-storing unit clamps and stores a voltage spike to obtain an energy-storing voltage. The feedback control unit detects the energy-storing voltage and informs the synchronous buck converter of the energy-storing voltage. The synchronous buck converter receives the energy-storing voltage and adjusts the energy-storing voltage to obtain an adjusted voltage when the energy-storing voltage is greater than a predetermined voltage. The synchronous buck converter sends the adjusted voltage to the voltage output side.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 26, 2017
    Inventors: Man-Chuen WONG, Wing-Kai CHOW
  • Patent number: 9312240
    Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: April 12, 2016
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Kriangsak Sae Le, Chee Kay Chow
  • Publication number: 20160078058
    Abstract: A system provides via a software application, a file sub-system that organizes images of an event for evaluation of an object or event as the object or event changes over time. A base image may be established and other images of the object or event may be co-related to the base image so that a user may select the base image for display along with the other images showing time lapsed changes to the object or event.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 17, 2016
    Inventor: Ching-Kay Chow
  • Publication number: 20160065896
    Abstract: Systems and methods provide location of an object via video conferencing. The systems and methods may be useful for applications that require remote assistance from an individual to help another individual locate an object or a feature within an image displayed on screen. The user of a local device may view the remote image for context of the environment. In some embodiments, the local user may help direct the remote user by directions to zoom in or out of the displayed image and may provide a frame to guide the remote user. A position in the remote image shown in the remote device is activated and displayed by the local user as an icon to help pinpoint the object location for the remote user.
    Type: Application
    Filed: September 2, 2015
    Publication date: March 3, 2016
    Inventor: Ching-Kay Chow