Patents by Inventor Kai Di Feng
Kai Di Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9503106Abstract: An integrated circuit includes a frequency-locked voltage regulated loop that further includes a voltage controlled oscillator (VCO), a frequency divider that generates sequential timing signals based on a period of the VCO from a frequency divided VCO signal, a frequency-to-voltage converter (FVC) that converts the frequency divided VCO signal into an output voltage, FVCOUT, an internal reference voltage, and a voltage regulator that generates a control voltage, VCOIN, that is fed back to the VCO to lock a frequency of the VCO in the frequency-locked voltage regulated loop.Type: GrantFiled: December 11, 2015Date of Patent: November 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Hanyi Ding, Kai Di Feng
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Patent number: 9252794Abstract: An on-chip frequency calibration apparatus is described. A ring oscillator generates a clock signal. A trimmable resistor is coupled to the ring oscillator. A frequency detector detects the frequency of the clock signal generated from the ring oscillator. The frequency detector includes a frequency divider component that divides the frequency of the clock signal by a predetermined number to derive an output signal having a pulse duration that is equal to at least one period of the clock signal, a capacitor, a capacitor charging current source, and a capacitor charge transistor directs a charging current generated from the capacitor charging current source to the capacitor as a function of the output signal generated from the frequency divider component. A resistor trimming unit trims the trimmable resistor in response to determining that the frequency detected by the frequency detector is less than a target frequency threshold.Type: GrantFiled: September 12, 2014Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Kai Di Feng, David R. Hanson, Chengwen Pei, Ping-Chuan Wang
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Patent number: 9189654Abstract: A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.Type: GrantFiled: December 4, 2013Date of Patent: November 17, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai Di Feng, Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
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Publication number: 20150154421Abstract: A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.Type: ApplicationFiled: December 4, 2013Publication date: June 4, 2015Applicant: International Business Machines CorporationInventors: Kai Di Feng, Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
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Patent number: 9013202Abstract: A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.Type: GrantFiled: May 23, 2012Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Fen Chen, Kai Di Feng, Pui Ling Yee
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Publication number: 20130314119Abstract: A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen Chen, Kai Di Feng, Pui Ling Yee
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Patent number: 8338920Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.Type: GrantFiled: May 8, 2007Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: John Michael Cotte, Hanyi Ding, Kai Di Feng, Zhong-Xiang He, Nils D. Hoivik, Xuefeng Liu
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Patent number: 8211756Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: GrantFiled: June 24, 2010Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 8122395Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.Type: GrantFiled: August 20, 2008Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventor: Kai Di Feng
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Patent number: 8086974Abstract: In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator.Type: GrantFiled: July 21, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventor: Kai Di Feng
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Patent number: 7961032Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×le×VCER)], VCER=VBER+VCBR, and le=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the trType: GrantFiled: November 30, 2009Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Zhijian Yang, Ping-Chuan Wang, Kai Di Feng
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Patent number: 7962322Abstract: A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.Type: GrantFiled: June 9, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Elie Awad, Mariette Awad, Kai Di Feng
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Publication number: 20110128069Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×1e×VCER], VCER=VBER+VCBR, and 1e=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the traType: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhijian Yang, Ping-Chuan Wang, Kai Di Feng
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Patent number: 7930664Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: GrantFiled: September 20, 2010Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7926015Abstract: In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented.Type: GrantFiled: July 21, 2008Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventor: Kai Di Feng
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Publication number: 20110034021Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: ApplicationFiled: September 20, 2010Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7886237Abstract: A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor.Type: GrantFiled: June 9, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Elie Awad, Mariette Awad, Kai Di Feng
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Patent number: 7839163Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: GrantFiled: January 22, 2009Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7816945Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: GrantFiled: January 22, 2009Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20100261318Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.Type: ApplicationFiled: June 24, 2010Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Kai Di Feng, Louis Lu-Chen Hsu, Ping-Chuan Wang, Zhijian Yang