Patents by Inventor Kai Frohberg

Kai Frohberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor having a high-k metal gate stack and a compressively stressed channel
    Patent number: 8017504
    Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 13, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Kai Frohberg
  • CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES COMPRISING A CONTINUOUS TRANSITION TO METAL LINES OF A METALLIZATION LAYER
    Publication number: 20110210447
    Abstract: In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer.
    Type: Application
    Filed: November 4, 2010
    Publication date: September 1, 2011
    Inventors: Robert Seidel, Kai Frohberg, Carsten Peters
  • Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing
    Publication number: 20110201135
    Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 18, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Frank Feustel, Thomas Werner, Kai Frohberg
  • Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process
    Patent number: 7998823
    Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: August 16, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carsten Peters, Kai Frohberg, Ralf Richter
  • SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOGRAPHY TOLERANT CONTACT STRUCTURE
    Publication number: 20110186929
    Abstract: In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided.
    Type: Application
    Filed: October 29, 2010
    Publication date: August 4, 2011
    Inventors: Jens Heinrich, Kai Frohberg, Kerstin Ruttloff
  • SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE WINDOW AREA
    Publication number: 20110189825
    Abstract: In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.
    Type: Application
    Filed: October 28, 2010
    Publication date: August 4, 2011
    Inventors: Jens Heinrich, Kai Frohberg, Sven Mueller, Kerstin Ruttloff
  • Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics
    Patent number: 7989352
    Abstract: By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: August 2, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • Fabricating vias of different size of a semiconductor device by splitting the via patterning process
    Patent number: 7977237
    Abstract: When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: July 12, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Feustel, Thomas Werner, Kai Frohberg
  • Method of reducing contamination by providing a removable polymer protection film during microstructure processing
    Patent number: 7955962
    Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: June 7, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Frank Feustel, Thomas Werner, Kai Frohberg
  • SEMICONDUCTOR DEVICE COMPRISING REPLACEMENT GATE ELECTRODE STRUCTURES WITH AN ENHANCED DIFFUSION BARRIER
    Publication number: 20110101426
    Abstract: In sophisticated semiconductor devices, the integrity of the device level may be enhanced after applying a replacement gate approach by providing an additional diffusion barrier layer, such as a silicon nitride layer, thereby obtaining a similar degree of diffusion blocking capabilities as in semiconductor devices without performing a replacement gate approach.
    Type: Application
    Filed: September 30, 2010
    Publication date: May 5, 2011
    Inventors: Kai Frohberg, Frank Feustal, Thomas Werner
  • SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES
    Publication number: 20110101460
    Abstract: In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment.
    Type: Application
    Filed: September 30, 2010
    Publication date: May 5, 2011
    Inventors: Jens Heinrich, Ralf Richter, Kai Frohberg
  • FABRICATING VIAS OF DIFFERENT SIZE OF A SEMICONDUCTOR DEVICE BY SPLITTING THE VIA PATTERNING PROCESS
    Publication number: 20110104867
    Abstract: When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences.
    Type: Application
    Filed: September 30, 2010
    Publication date: May 5, 2011
    Inventors: Frank Feustel, Thomas Werner, Kai Frohberg
  • Field effect transistor having a stressed contact etch stop layer with reduced conformality
    Patent number: 7932166
    Abstract: By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a non-conformal manner, thereby achieving higher transistor performance for otherwise identical stress conditions.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: April 26, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Frank Feustel, Thomas Werner
  • SEMICONDUCTOR DEVICE COMPRISING A BURIED WAVEGUIDE FOR DEVICE INTERNAL OPTICAL COMMUNICATION
    Publication number: 20110076028
    Abstract: In an integrated circuit device, such as a microprocessor, a device internal optical communication system is provided in order to enhance signal transfer capabilities while relaxing overall thermal conditions. Furthermore, the device internal optical data or signal transfer capabilities may result in superior operating speed and a high degree of design flexibility. The optical communication system may be applied as a chip internal system in single chip systems or as an inter-chip optical system in three-dimensional chip configurations provided in a single package.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 31, 2011
    Inventors: Uwe Griebenow, Kai Frohberg, Jan Hoentschel
  • STRESS ENGINEERING IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES BY STRESSED CONDUCTIVE LAYERS AND AN ISOLATION SPACER
    Publication number: 20110073959
    Abstract: In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 31, 2011
    Inventors: Kai Frohberg, Hartmut Ruelke, Volker Jaschke, Joerg Hohage, Frank Seliger
  • Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines
    Patent number: 7910496
    Abstract: By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: March 22, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Carsten Peters
  • Increased reliability for a contact structure to connect an active region with a polysilicon line
    Patent number: 7906815
    Abstract: By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: March 15, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carsten Peters, Ralf Richter, Kai Frohberg
  • Semiconductor device comprising a contact structure based on copper and tungsten
    Patent number: 7902581
    Abstract: By providing contact plugs having a lower plug portion, formed on the basis of well-established tungsten-based technologies, and an upper plug portion, which may comprise a highly conductive material such as copper or a copper alloy, a significant increase in conductivity of the contact structure may be achieved. For this purpose, after the deposition of a first dielectric layer of the inter-layer stack, a planarization process may be performed so as to allow the formation of the lower plug portions on the basis of tungsten, while, after the deposition of the second dielectric layer, a corresponding copper-based technology may be used for forming the upper plug portions of significantly enhanced conductivity.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: March 8, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Carsten Peters, Thomas Werner
  • SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER
    Publication number: 20110049640
    Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.
    Type: Application
    Filed: August 11, 2010
    Publication date: March 3, 2011
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • DUAL CONTACT METALLIZATION INCLUDING ELECTROLESS PLATING IN A SEMICONDUCTOR DEVICE
    Publication number: 20110049713
    Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.
    Type: Application
    Filed: August 11, 2010
    Publication date: March 3, 2011
    Inventors: Kai Frohberg, Juergen Boemmels, Matthias Schaller, Sven Mueller