Abstract: The present invention relates to an optimal load curtailment calculating method based on Lagrange multiplier and an application thereof in power system reliability assessment, wherein the calculating method comprises the following steps: inputting all system states to be analyzed for reliability assessment and establishing corresponding optimal load curtailment models; classifying the optimal load curtailment models according to Lagrange multiplier to obtain several sets; and solving the optimal load curtailment models in each set by using Lagrange multipliers to obtain an optimal load curtailment corresponding to the system state. The core of the present invention is to establish Lagrange-multiplier-based linear functions between the optimal load curtailment and the system states, and the iterative optimization processes of the traditional optimal load curtailment calculating method are substituted with the simple matrix multiplications.

Abstract: An array substrate and a display panel are provided. The array substrate includes: a plurality of sub-pixels arranged along a row direction and a column direction, four or six adjacent sub-pixel columns constituting a sub-pixel column group; a plurality of data lines extending along the column direction and comprising a first data line and a second data line. In the row direction, the first data line and the second data line are respectively provided on two sides of the sub-pixel column group, and a data line pair including the first data line and the second data line is located between adjacent sub-pixel column groups.

Abstract: A display panel and a display device are provided. The display panel includes a first substrate and a second substrate. The first substrate includes: a first base substrate; and a plurality of spacers on the first base substrate, including a first sub spacer and a second sub spacer; and the second substrate includes: a second base substrate; a gate line; a plurality of sub-pixels on the second base substrate; a first boss and a second boss on the second base substrate. The second substrate includes a first row of pixels and a second row of pixels adjacent to the first row of pixels; an orthographic projection of the second boss and an orthographic projection of the gate line on the second base substrate overlap; an orthographic projection of the first sub spacer and an orthographic projection of the first boss on the second base substrate at least partially overlap.

Abstract: The disclosure provides a display substrate and a manufacturing method thereof, a display panel and a display apparatus. The display substrate includes a substrate and an electroluminescent layer on the substrate. The display substrate further includes a first reflective electrode layer, a buffer layer and a second reflective electrode layer sequentially formed on a side of the electroluminescent layer distal to the substrate. The buffer layer is provided with a first hollow region, the second reflective electrode layer is provided with a second hollow region, an overlapping region between the first hollow region and the second hollow region is configured to transmit light emitted by the electroluminescent layer. The present disclosure can detect the light-emitting brightness of each sub-pixel in the organic electroluminescent layer in real time to improve light-emitting efficiency.

Abstract: A phase shifter, a phase shift degree compensation device, and a phase shift degree compensation method are provided.

Abstract: An array substrate and a display panel are provided. The array substrate includes: a plurality of sub-pixels arranged along a row direction and a column direction, four or six adjacent sub-pixel columns constituting a sub-pixel column group; a plurality of data lines extending along the column direction and comprising a first data line and a second data line. In the row direction, the first data line and the second data line are respectively provided on two sides of the sub-pixel column group, and a data line pair including the first data line and the second data line is located between adjacent sub-pixel column groups.

Abstract: The present disclosure relates to a display panel and a manufacturing method thereof, a display device. The display panel includes an array substrate and a color film substrate set oppositely, the array substrate includes multiple subpixel units arranged in an array and an orientation layer covering multiple subpixel units, each subpixel unit includes an opening area; the color film substrate is provided with support columns, orthographic projections of the support columns on the subpixel units are outside the opening areas, the orientation layer is formed with support protrusions which protrude from a surface of the orientation layer, orthographic projections of the support protrusions on the subpixel units are outside the opening areas, the support columns contact top ends of the support protrusions to prevent the support columns from contacting the surface of the orientation layer.

Abstract: Disclosed are an array substrate, a fabrication method thereof, a liquid crystal display panel and a display device. The array substrate includes a substrate, a wire grid polarization layer located in an open region in a pixel region of the substrate and a transparent pattern located at the side, away from the substrate, of the wire grid polarization layer and consistent with a pattern of the wire grid polarization layer.

Abstract: A reflective display panel includes an array substrate and an opposite substrate disposed, wherein a photoelectric material layer is disposed between the array substrate and the opposite substrate, and the reflective display panel is divided into a plurality of pixel areas, both a solar cell layer and a light adjustment layer are disposed on a side of the photoelectric material layer, and the light adjustment layer is disposed between the solar cell layer and the photoelectric material layer, and the light adjustment layer comprises a light adjustment portion located in each of the pixel areas, and the light adjustment portion, when the pixel area is in a display state, reflects at least a part of light emitted from the photoelectric material layer toward the light adjustment portion, and when the pixel area is in a non-display state, transmits the light emitted from the photoelectric material layer.

Abstract: The present disclosure relates to a display panel and a manufacturing method thereof, a display device. The display panel includes an array substrate and a color film substrate set oppositely, the array substrate includes multiple subpixel units arranged in an array and an orientation layer covering multiple subpixel units, each subpixel unit includes an opening area; the color film substrate is provided with support columns, orthographic projections of the support columns on the subpixel units are outside the opening areas, the orientation layer is formed with support protrusions which protrude from a surface of the orientation layer, orthographic projections of the support protrusions on the subpixel units are outside the opening areas, the support columns contact top ends of the support protrusions to prevent the support columns from contacting the surface of the orientation layer.

Abstract: The present invention discloses an impact increments-based state enumeration (IISE) reliability assessment approach and device thereof. The method includes: inspecting the accessibility of all elements of the independent adjacency matrix by the breadth-first search method; if there is inaccessible element, the impact increment is zero and the power system state is reselected; if there is no inaccessible element, evaluating the impact of the power system state under all load levels via optimal power flow algorithm, acquiring the impact expectations of power system state under different load levels, and then acquiring the impact increments of the power system state; acquiring the reliability index of power system by impact increment when all the centralized power system states have been analyzed and the maximum number of contingency order has reached.

Abstract: A power supply system used in an electronic device includes a light absorption device, exposed to a backlight source of the electronic device, for absorbing backlight irradiated by the backlight source; an energy conversion circuit, coupled to the light absorption device, for converting the backlight irradiated by the backlight source into electrical power; and a power storage device, coupled to the energy conversion circuit, for storing the electrical power of the energy conversion circuit.

Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.

Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

Abstract: In a chip packaging process, an upper and a lower mold chases are provided. A thickness adjusting film is then provided below the upper mold chase and/or above the lower mold chase. Next, a carrier is delivered to a position between the upper and the lower mold chases. A chip and a conductive line are disposed on the carrier, and the thickness adjusting film is located between the upper mold chase and the carrier and/or between the lower mold chase and the carrier. The upper and the lower mold chases are attached to define a cavity, and the thickness adjusting film is located on the surface of the upper mold chase and/or the surface of the lower mold chase. Thereafter, a molding compound is provided into the cavity by using a molding compound supplying unit. The upper and the lower mold chases and the thickness adjusting film are removed.

Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.

Abstract: A chip packaging apparatus including an upper mold chase, a lower mold chase, a carrier delivering unit, a molding compound thickness adjusting unit, and a molding compound supplying unit is provided. The lower mold chase is disposed below the upper mold chase. The carrier delivering unit delivers a carrier to a position between the upper mold chase and the lower mold chase. The molding compound thickness adjusting unit provides a thickness adjusting film between the upper mold chase and the carrier and/or between the lower mold chase and the carrier, and adjusts the thickness of the molding compound according to the thickness of the thickness adjusting film. The molding compound supplying unit is connected to the upper mold chase or the lower mold chase for providing the molding compound into a cavity defined by the upper mold chase and the lower mold chase.

Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, an insulating layer, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The insulating layer is filled in a plurality of slots between the package areas. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place.

Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of first slots, a plurality of first side rails, a plurality of second side rails, and tape. Each of the package areas comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of first side rails and the plurality of second side rails are connected and surround the plurality of the package areas. The tape fixes the plurality of package areas, the plurality of first side rails, the plurality of second side rails, the die pads, and the plurality of leads in place.