Patents by Inventor Kai Hou

Kai Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180375373
    Abstract: The present invention discloses an impact increments-based state enumeration (IISE) reliability assessment approach and device thereof. The method includes: inspecting the accessibility of all elements of the independent adjacency matrix by the breadth-first search method; if there is inaccessible element, the impact increment is zero and the power system state is reselected; if there is no inaccessible element, evaluating the impact of the power system state under all load levels via optimal power flow algorithm, acquiring the impact expectations of power system state under different load levels, and then acquiring the impact increments of the power system state; acquiring the reliability index of power system by impact increment when all the centralized power system states have been analyzed and the maximum number of contingency order has reached.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 27, 2018
    Applicant: Tianjin University
    Inventors: Hongjie JIA, Kai HOU, Yunfei MU, Xiaodan Yu
  • Publication number: 20140368034
    Abstract: A power supply system used in an electronic device includes a light absorption device, exposed to a backlight source of the electronic device, for absorbing backlight irradiated by the backlight source; an energy conversion circuit, coupled to the light absorption device, for converting the backlight irradiated by the backlight source into electrical power; and a power storage device, coupled to the energy conversion circuit, for storing the electrical power of the energy conversion circuit.
    Type: Application
    Filed: September 24, 2013
    Publication date: December 18, 2014
    Applicant: Wistron Corporation
    Inventors: Yuan-Tai Chen, Kai-Hou Lin, Shao-Huai Tsai, Kai-Yu Chu, Yu-Han Tsai
  • Patent number: 7842550
    Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 30, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Chun-Ying Lin, Geng-Shin Shen, Po-Kai Hou
  • Patent number: 7812432
    Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: October 12, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Po-Kai Hou, Chi-Jin Shih
  • Publication number: 20100120201
    Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.
    Type: Application
    Filed: December 11, 2008
    Publication date: May 13, 2010
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Chun-Ying Lin, Geng-Shin Shen, Po-Kai Hou
  • Publication number: 20090321988
    Abstract: In a chip packaging process, an upper and a lower mold chases are provided. A thickness adjusting film is then provided below the upper mold chase and/or above the lower mold chase. Next, a carrier is delivered to a position between the upper and the lower mold chases. A chip and a conductive line are disposed on the carrier, and the thickness adjusting film is located between the upper mold chase and the carrier and/or between the lower mold chase and the carrier. The upper and the lower mold chases are attached to define a cavity, and the thickness adjusting film is located on the surface of the upper mold chase and/or the surface of the lower mold chase. Thereafter, a molding compound is provided into the cavity by using a molding compound supplying unit. The upper and the lower mold chases and the thickness adjusting film are removed.
    Type: Application
    Filed: September 8, 2009
    Publication date: December 31, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: Po-Kai Hou
  • Publication number: 20090224384
    Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.
    Type: Application
    Filed: November 11, 2008
    Publication date: September 10, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: Po-Kai Hou, Chi-Jin Shih
  • Publication number: 20090206519
    Abstract: A chip packaging apparatus including an upper mold chase, a lower mold chase, a carrier delivering unit, a molding compound thickness adjusting unit, and a molding compound supplying unit is provided. The lower mold chase is disposed below the upper mold chase. The carrier delivering unit delivers a carrier to a position between the upper mold chase and the lower mold chase. The molding compound thickness adjusting unit provides a thickness adjusting film between the upper mold chase and the carrier and/or between the lower mold chase and the carrier, and adjusts the thickness of the molding compound according to the thickness of the thickness adjusting film. The molding compound supplying unit is connected to the upper mold chase or the lower mold chase for providing the molding compound into a cavity defined by the upper mold chase and the lower mold chase.
    Type: Application
    Filed: November 10, 2008
    Publication date: August 20, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: Po-Kai Hou
  • Publication number: 20090127684
    Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, an insulating layer, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The insulating layer is filled in a plurality of slots between the package areas. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 21, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: HENG CHANG KUO, PO KAI HOU, CHUN YING LIN
  • Publication number: 20090108419
    Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, a plurality of connection portions, a plurality of openings, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The plurality of connection portions connect the plurality of package areas. The plurality of openings are disposed on the plurality of connection portions, and are aligned with some of the plurality of slots. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 30, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: HENG CHANG KUO, PO KAI HOU, CHUN YING LIN
  • Publication number: 20090108424
    Abstract: A leadframe for a leadless package comprises a plurality of package areas, a plurality of first slots, a plurality of first side rails, a plurality of second side rails, and tape. Each of the package areas comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of first side rails and the plurality of second side rails are connected and surround the plurality of the package areas. The tape fixes the plurality of package areas, the plurality of first side rails, the plurality of second side rails, the die pads, and the plurality of leads in place.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 30, 2009
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventors: HENG CHANG KUO, PO KAI HOU, CHUN YING LIN
  • Patent number: 5983997
    Abstract: A system for cooling electronic components includes a cold plate having a channel through which a fluid coolant is transported, a plurality of bosses each receiving an electronic, optical, or other heat-generating component, and a plurality of fin structures, at least three of which are adjacently disposed in a sequential order on the cold plate. Each fin structure contacts a boss, and has a fin inlet and a fin outlet in fluid communication with a section of the channel for supplying the area around the boss with coolant and cooling the component seated on the boss. A portion of the channel defines a serpentine path for transporting the fluid coolant to the at least three sequential fin structures in a non-sequential order. Sections of the channel in the serpentine path further transport the coolant in opposite directions, thus enhancing heat transfer and temperature equilibration across the cold plate.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: November 16, 1999
    Assignee: Brazonics, Inc.
    Inventor: Kai Hou
  • Patent number: 5946803
    Abstract: A method for making a ultra-thin fin heat sink includes the following steps. First, a continuous elongated heat sink bar is made by, the extrusion procedure wherein such heat sink bar is formed with a plurality of parallel closely spaced ultra-thin fins integrally extending from a base. Liquid type wax is injected into the space between every two adjacent fins until such space is completely filled with the wax. The wax is solidified after a while, and then the whole assembly including the heat sink bar with the inner wax generally becomes a whole solid reinforced structure which can bear the traditional sawing procedure. Via a fixture, the assembly is sawed/cut to pieces of the predetermined length. The cut pieces are successively heated to have the inner solid wax liquefied and leave from the heat sink unit.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: September 7, 1999
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Kai Hou
  • Patent number: 5933325
    Abstract: A retaining clamp device (10) for use with a heat sink (40) of the CPU (50) unit includes a clip (12) and an associated spring (30) attached to the clip (12) wherein the clip (12) includes an elongated main body (14) with a pair of locking tags (18) downward extending at two opposite ends thereof to respectively cooperate with the lugs (62) on the side walls (64) of the socket (60) under the CPU (50) for latching the retaining clamp device (10) unto the CPU (50) set while the spring (30) is in a wave-like form and positioned between the main body (14) of the clip (12) and the top surface (48) of the heat sink (40) so as to exert the sufficient biasing force firmly pressing the heat sink (40) against the CPU (50) for efficient heat transfer thereof, by means of its deformation derived from the less space/height between the main body (14) of the clip (12) and the top surface (48) of the heat sink (40) in comparison with the original height of the spring (30).
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: August 3, 1999
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Kai Hou