Patents by Inventor Kai-Hung Cheng
Kai-Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10777466Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: GrantFiled: March 15, 2018Date of Patent: September 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Jaming Chang, Jei Ming Chen, Kai Hung Cheng
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Patent number: 10734227Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.Type: GrantFiled: June 3, 2019Date of Patent: August 4, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
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Patent number: 10720430Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: GrantFiled: December 26, 2019Date of Patent: July 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Publication number: 20200144258Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: ApplicationFiled: December 26, 2019Publication date: May 7, 2020Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Publication number: 20200075320Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.Type: ApplicationFiled: June 3, 2019Publication date: March 5, 2020Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
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Patent number: 10522541Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: GrantFiled: April 22, 2019Date of Patent: December 31, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Publication number: 20190252379Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Publication number: 20190164844Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: ApplicationFiled: March 15, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wen HUANG, Chia-Hui LIN, Jaming CHANG, Jei Ming CHEN, Kai Hung CHENG
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Patent number: 10269796Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: GrantFiled: January 10, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Publication number: 20180130800Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: ApplicationFiled: January 10, 2018Publication date: May 10, 2018Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Patent number: 9881918Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: GrantFiled: September 30, 2016Date of Patent: January 30, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Publication number: 20170319723Abstract: Disclosed herein is a radioimmune complex comprising an epidermal growth factor receptor (EGFR)-targeted antibody and a radioactive isotope of rhenium labeled thereon. The EGFR-targeted antibody is cetuximab or panitumumab.Type: ApplicationFiled: May 3, 2017Publication date: November 9, 2017Inventors: WAN-I KUO, KAI-HUNG CHENG, YI-SHU HUANG, SHENG-NAN LO, YA-JEN CHANG, TSUNG-TSE WU, WEI-CHUAN HSU, MING-HSIN LI, CHIH-HSIEN CHANG
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Patent number: 9541699Abstract: A backlight module including a back plate, a light guide plate, a light source, a plastic frame, and a light conversion layer is provided. The light guide plate is disposed on the back plate and has a light incident surface and a light exit surface, wherein a first edge of the light exit surface is adjacent to the light incident surface. The light source is disposed on the back plate and faces the light incident surface. The plastic frame is disposed on the back plate and covers the first edge. The light conversion layer is disposed on the light exit surface and extends to the first edge.Type: GrantFiled: February 4, 2015Date of Patent: January 10, 2017Assignee: Young Lighting Technology Inc.Inventors: Kai-Hung Cheng, Chia-Hung Yu
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Publication number: 20160016958Abstract: Flumazenil (FMZ) is labeled with fluorine(F)-18 to obtain F-18-flumazenil. F-18-flumazenil can be strongly combined with type-A acceptor of gamma-aminobutyric acid (GABAA) in brain for tracing. The time and temperature for labeling is saved and lowered. The toxic chemical, acetonitrile, used in separation and purification can be prevented. The present invention has a simplified procedure for evaluating mental disease medicines in a short time. Moreover, time for developing medicines for treating related diseases of the central nervous system can be reduced.Type: ApplicationFiled: July 17, 2014Publication date: January 21, 2016Inventors: Kai-Hung Cheng, Yean-Hung Tu, Li-Yuan Huang, Yuan-Ruei Huang, Kang-Wei Chang
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Publication number: 20150331170Abstract: A backlight module including a back plate, a light guide plate, a light source, a plastic frame, and a light conversion layer is provided. The light guide plate is disposed on the back plate and has a light incident surface and a light exit surface, wherein a first edge of the light exit surface is adjacent to the light incident surface. The light source is disposed on the back plate and faces the light incident surface. The plastic frame is disposed on the back plate and covers the first edge. The light conversion layer is disposed on the light exit surface and extends to the first edge.Type: ApplicationFiled: February 4, 2015Publication date: November 19, 2015Applicant: YOUNG LIGHTING TECHNOLOGY INC.Inventors: Kai-Hung Cheng, Chia-Hung Yu
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Publication number: 20130074239Abstract: A apron having a one-piece thin sheet body made from a flexible and foldable material and properly cut to provide an open type neckline portion disposed in a middle part near the top side thereof for attaching to the user's neck, two back belts respectively formed of a left part and a right part thereof for tying the apron to the user's waist, and two neck belts respectively formed of a top left part and a top right part thereof for tying the apron to the user's neck, and thus the apron can be better secured to the user's body to well protect the user's clothes from “wear and tear”.Type: ApplicationFiled: August 24, 2012Publication date: March 28, 2013Inventors: Yung Chu CHENG, Yu Liang Cheng, Kai Hung Cheng
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Patent number: 8328378Abstract: Provided are a package, a light uniformization structure, and a backlight module using same. The package helps improving uniformity of light and includes a multi-lateral transparent body, which has a top face and lateral faces, which are all planar surfaces. The transparent body has a bottom face in which a semispherical cavity is formed and extends inward into the body. With the package capped over a light-emitting diode with semispherical cavity set to correspond to the light-emitting diode, the light shape and the energy of light from the light-emitting diode is re-distribution and utilized by the package to thereby provide a light uniformization structure that shows high brightness, high performance, and high uniformity of light. One or a plurality of such light uniformization structures can be provided on a backlight module to enhance light uniformity for a displaying panel.Type: GrantFiled: July 20, 2010Date of Patent: December 11, 2012Assignee: National Changhua University of EducationInventors: Jin-Jia Chen, Kai-Hung Cheng, Kuang-Lung Huang
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Publication number: 20120020053Abstract: Provided are a package, a light uniformization structure, and a backlight module using same. The package helps improving uniformity of light and includes a multi-lateral transparent body, which has a top face and lateral faces, which are all planar surfaces. The transparent body has a bottom face in which a semispherical cavity is formed and extends inward into the body. With the package capped over a light-emitting diode with semispherical cavity set to correspond to the light-emitting diode, the light shape and the energy of light from the light-emitting diode is re-distribution and utilized by the package to thereby provide a light uniformization structure that shows high brightness, high performance, and high uniformity of light. One or a plurality of such light uniformization structures can be provided on a backlight module to enhance light uniformity for a displaying panel.Type: ApplicationFiled: July 20, 2010Publication date: January 26, 2012Inventors: JIN-JIA CHEN, Kai-Hung Cheng, Kuang-Lung Huang