Patents by Inventor Kai-Ling Chiu
Kai-Ling Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118178Abstract: A staining kit is provided, including a first pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, CD8, CD45, and CTLA4; a second pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, dendritic cell, and CD45; a third pattern including antibodies against T cell, B cell, NK cell, monocyte, CD8, CD45, CD45RA, CD62L, CD197, CX3CR1 and TCR??; and a fourth pattern including antibodies against B cell, CD23, CD38, CD40, CD45 and IgM, wherein the antibodies of each pattern are labeled with fluorescent dyes. A method of identifying characterized immune cell subsets of a disease and a method of predicting the likelihood of NPC in a subject in the need thereof using the staining kit are also provided.Type: ApplicationFiled: October 5, 2022Publication date: April 11, 2024Applicant: FULLHOPE BIOMEDICAL CO., LTD.Inventors: Jan-Mou Lee, Li-Jen Liao, Yen-Ling Chiu, Chih-Hao Fang, Kai-Yuan Chou, Pei-Hsien Liu, Cheng-Yun Lee
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Publication number: 20230013188Abstract: Structures and related techniques for singulating GaN-on-Si wafers are disclosed. In one aspect, a semiconductor wafer includes a silicon layer, and a gallium nitride (GaN) layer disposed on the silicon layer and defining a plurality of trenches that each extend to the silicon layer. In another aspect, the GaN layer includes one or more gallium nitride layers of different compositions. In yet another aspect, the wafer includes a plurality of dielectric layers disposed on the GaN layer. In yet another aspect, each of the plurality of trenches has a depth that is equal to a sum of a thickness of the GaN layer and a thickness of the plurality of the dielectric layers.Type: ApplicationFiled: July 13, 2022Publication date: January 19, 2023Applicant: Navitas Semiconductor LimitedInventors: George Chu, Nick Fichtenbaum, Kai-Ling Chiu, Daniel M. Kinzer, Maher Hamdan, Pil Sung Park
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Patent number: 9543222Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.Type: GrantFiled: May 29, 2015Date of Patent: January 10, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ling Chiu, Tse-Hua Lu, Yu-Kuo Cheng, Po-Chun Chiu, Ping-Fang Hung
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Patent number: 9277195Abstract: This disclosure provides pixel arrays made up of a clear pixel and a color pixel. The color pixel includes a first photo-detecting element and a color pixel access transistor to selectively couple the first photo-detecting element to a first charge-storage node. The clear pixel includes a second photo-detecting element and a clear pixel access transistor to selectively couple the second photo-detecting element to a second charge-storage node. The color pixel access transistor transfers a first charge per unit time between the first photo-detecting element and the first charge-storage node. The clear pixel access transistor transfers a second charge per unit time between the clear pixel access transistor and the second charge-storage node. The first charge per unit time is less than the second charge per unit time to mitigate blooming. In other embodiments, the clear pixel includes an excess-charge transfer path that couples the clear pixel to a DC supply node to mitigate blooming.Type: GrantFiled: April 8, 2014Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Ling Chiu, Masayuki Uchiyama, Po-Chun Chiu, Tse-Hua Lu, Yuichiro Yamashita
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Publication number: 20150288940Abstract: This disclosure provides pixel arrays made up of a clear pixel and a color pixel. The color pixel includes a first photo-detecting element and a color pixel access transistor to selectively couple the first photo-detecting element to a first charge-storage node. The clear pixel includes a second photo-detecting element and a clear pixel access transistor to selectively couple the second photo-detecting element to a second charge-storage node. The color pixel access transistor transfers a first charge per unit time between the first photo-detecting element and the first charge-storage node. The clear pixel access transistor transfers a second charge per unit time between the clear pixel access transistor and the second charge-storage node. The first charge per unit time is less than the second charge per unit time to mitigate blooming. In other embodiments, the clear pixel includes an excess-charge transfer path that couples the clear pixel to a DC supply node to mitigate blooming.Type: ApplicationFiled: April 8, 2014Publication date: October 8, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Ling Chiu, Masayuki Uchiyama, Po-Chun Chiu, Tse-Hua Lu, Yuichiro Yamashita
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Publication number: 20150262891Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.Type: ApplicationFiled: May 29, 2015Publication date: September 17, 2015Inventors: Kai-Ling Chiu, Tse-Hua Lu, Yu-Kuo Cheng, Po-Chun Chiu, Ping-Fang Hung
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Patent number: 9048126Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.Type: GrantFiled: May 10, 2013Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ling Chiu, Tse-Hua Lu, Yu-Kuo Cheng, Po-Chun Chiu, Ping-Fang Hung
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Patent number: 9041155Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.Type: GrantFiled: September 9, 2013Date of Patent: May 26, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
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Publication number: 20140264505Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.Type: ApplicationFiled: May 10, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ling Chiu, Tse-Hua Lu, Yu-Kuo Cheng, Po-Chun Chiu, Ping-Fang Hung
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Patent number: 8716802Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: GrantFiled: August 9, 2010Date of Patent: May 6, 2014Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Patent number: 8664705Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.Type: GrantFiled: May 29, 2012Date of Patent: March 4, 2014Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
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Patent number: 8637936Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.Type: GrantFiled: September 25, 2009Date of Patent: January 28, 2014Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
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Publication number: 20140008762Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.Type: ApplicationFiled: September 9, 2013Publication date: January 9, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
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Publication number: 20130320421Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.Type: ApplicationFiled: May 29, 2012Publication date: December 5, 2013Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
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Patent number: 8558346Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.Type: GrantFiled: June 26, 2012Date of Patent: October 15, 2013Assignee: United Microelectronics Corp.Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
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Patent number: 8477475Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.Type: GrantFiled: August 4, 2011Date of Patent: July 2, 2013Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Publication number: 20110292565Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.Type: ApplicationFiled: August 4, 2011Publication date: December 1, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Patent number: 8027144Abstract: A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes.Type: GrantFiled: April 28, 2009Date of Patent: September 27, 2011Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Publication number: 20110073957Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
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Publication number: 20100320540Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: ApplicationFiled: August 9, 2010Publication date: December 23, 2010Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh