Patents by Inventor Kai-Ling Chiu

Kai-Ling Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7803687
    Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor-Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Patent number: 7804154
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: September 28, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
  • Publication number: 20100148263
    Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 17, 2010
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: KAI-LING CHIU, CHIH-YU TSENG, VICTOR CHIANG LIANG, YOU-REN LIU, Chih-Chen Hsueh
  • Publication number: 20100099229
    Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 22, 2010
    Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor-Chiang Liang, You-Ren Liu, Chih-Chen Hsueh