Patents by Inventor Kai Mao

Kai Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12209013
    Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.
    Type: Grant
    Filed: August 6, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jhao-Yi Wang, Chin-Yu Ku, Wen-Hsiung Lu, Lung-Kai Mao, Ming-Da Cheng
  • Patent number: 12212926
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: January 28, 2025
    Assignee: FORTEMEDIA, INC.
    Inventors: Wen-Shan Lin, Chun-Kai Mao, Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Nai-Hao Kuo
  • Patent number: 12207052
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate. The opening portion of the substrate is under the diaphragm, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a pillar structure connected with the backplate and the diaphragm and a protection post structure extending from the backplate into the air gap. From a top view of the backplate, the protection post structure surrounds the pillar structure.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: January 21, 2025
    Assignee: FORTEMEDIA, INC.
    Inventors: Chun-Kai Mao, Chih-Yuan Chen, Feng-Chia Hsu, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
  • Publication number: 20240383744
    Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Jhao-Yi Wang, Chin-Yu Ku, Wen-Hsiung Lu, Lung-Kai Mao, Ming-Da Cheng
  • Patent number: 12134557
    Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jhao-Yi Wang, Chin-Yu Ku, Wen-Hsiung Lu, Lung-Kai Mao, Ming-Da Cheng
  • Publication number: 20240340598
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The backplate comprises a backplate conductive layer and a backplate insulating layer stacked with each other. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The MEMS structure further includes a pillar structure connected with the backplate. The pillar structure comprises a pillar conductive layer and a pillar insulating layer stacked with each other.
    Type: Application
    Filed: December 5, 2023
    Publication date: October 10, 2024
    Inventors: Chun-Kai MAO, Jien-Ming CHEN, Wen-Shan LIN, Nai-Hao KUO
  • Patent number: 12092478
    Abstract: According to a surveying and mapping instrument and method for a wide-area spatial channel map through multi-unmanned aerial vehicle (UAV) cooperation, a measurement signal emission unit generates and emits a measurement signal, a measurement signal multi-UAV cooperative receiving unit receives the measurement signal transmitted through a wireless channel, extracts an effective multipath component from the measurement signal, and frames the effective multipath component and corresponding time and location information for storage, and transmits stored channel data to a channel data fusion processing unit offline, and the channel data fusion processing unit fuses the channel data in terms of space, time, and frequency dimensions, and completes missing channel data to construct a complete wide-area spatial channel map.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: September 17, 2024
    Assignee: Nanjing University of Aeronautics and Astronautics
    Inventors: Qiuming Zhu, Kai Mao, Yanheng Qiu, Xiaomin Chen, Boyu Hua, Zhipeng Lin, Xuchao Ye, Weizhi Zhong, Fuqiao Duan, Qihui Wu
  • Patent number: 12096183
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a filler structure disposed on the diaphragm, and a portion of the filler structure is disposed in the ventilation hole.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: September 17, 2024
    Assignee: FORTEMEDIA, INC.
    Inventors: Chih-Yuan Chen, Feng-Chia Hsu, Chun-Kai Mao, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
  • Publication number: 20240290656
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Publication number: 20240283728
    Abstract: A method for predicting traffic suppression, an electronic device and a storage medium are disclosed. The method may include: determining a traffic value of suppression point according to a preset network traffic model which represents a mapping relationship between a numerical value of a network parameter of a transmission network and a traffic value, wherein the traffic value of suppression point is a traffic threshold of the transmission network under a current running policy; determining a suppression reference value of a target network parameter corresponding to the traffic value of suppression point; and acquiring a parameter prediction value corresponding to the target network parameter, and determining a traffic suppression prediction result according to the parameter prediction value and the suppression reference value.
    Type: Application
    Filed: May 23, 2022
    Publication date: August 22, 2024
    Inventors: Zepeng MA, Qiaoyan LIU, Kai MAO, Jianguo LI, Ke SHI
  • Publication number: 20240271961
    Abstract: According to a surveying and mapping instrument and method for a wide-area spatial channel map through multi-unmanned aerial vehicle (UAV) cooperation, a measurement signal emission unit generates and emits a measurement signal, a measurement signal multi-UAV cooperative receiving unit receives the measurement signal transmitted through a wireless channel, extracts an effective multipath component from the measurement signal, and frames the effective multipath component and corresponding time and location information for storage, and transmits stored channel data to a channel data fusion processing unit offline, and the channel data fusion processing unit fuses the channel data in terms of space, time, and frequency dimensions, and completes missing channel data to construct a complete wide-area spatial channel map.
    Type: Application
    Filed: July 31, 2023
    Publication date: August 15, 2024
    Applicant: Nanjing University of Aeronautics and Astronautics
    Inventors: Qiuming ZHU, Kai MAO, Yanheng QIU, Xiaomin CHEN, Boyu HUA, Zhipeng LIN, Xuchao YE, Weizhi ZHONG, Fuqiao DUAN, Qihui WU
  • Patent number: 12009256
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Patent number: 11999387
    Abstract: A heat dissipation system for a high-speed train running in a low-vacuum tube is provided. Component groups that provide power and resistance for the movement and stop of a train are provided at a periphery, close to the train, in a low-vacuum tube. The component group is provided with a group A cooling assembly. The group A cooling assembly includes a group A cooling-type heat exchanger and/or a group A nozzle assembly attached to the back of the component group. Since the friction between the train running at high speed and the air in the low-vacuum tube and the operation of the key equipment in the low-vacuum tube will generate a lot of heat, the group A cooling assembly in the component group in the low-vacuum tube exchanges the heat with the air in the low-vacuum tube.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 4, 2024
    Assignees: HEFEI GENERAL MACHINERY RESEARCH INSTITUTE CO., LTD, HEFEI GENERAL ENVIRONMENTAL CONTROL TECHNOLOGY CO., LTD, HIWING TECHNOLOGY ACADEMY OF CASIC
    Inventors: Xiuping Zhang, Panpan Zhao, Junfeng Wu, Ru Zhang, Xiaoming Kong, Shuangqing Xu, Dao Zhou, Xudong Yuan, Kai Mao, Na Zhang, Ming Zhao, Shaowei Li, Jinglong Bo
  • Publication number: 20240171359
    Abstract: The present application provides a model training method, a channel adjustment method, an electronic device, and a computer readable storage medium, the model training method includes: collecting historical samples, with the historical samples including first scheduling information and first information corresponding to a historical data transmission, the first information representing a result of cyclic redundancy check, and the first scheduling information including first intermediate variable information in an adaptive modulation and coding process; and performing model training according to the historical samples to obtain a first prediction model, and during the model training, the first scheduling information is used as an input of the first prediction model, the first information is converted into second information corresponding to the historical data transmission to be used as an output of the first prediction model, and the second information represents a probability value of the result of the cycli
    Type: Application
    Filed: March 14, 2022
    Publication date: May 23, 2024
    Inventors: Dexin LI, Qiaoyan LIU, Kai MAO, Jianguo LI, Wangwang JI, Zepeng MA, Ke SHI
  • Publication number: 20240153849
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a chip structure including a substrate and a wiring structure over a first surface of the substrate. The semiconductor device structure includes a first seed layer over the wiring structure, a first inner wall of the first enlarged portion, and a second inner wall of the neck portion. The semiconductor device structure includes a second seed layer over a second surface of the substrate, a third inner wall of the second enlarged portion, and the first seed layer over the second inner wall of the neck portion. The second seed layer is in direct contact with the first seed layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li YANG, Wen-Hsiung LU, Lung-Kai MAO, Fu-Wei LIU, Mirng-Ji LII
  • Publication number: 20240120207
    Abstract: A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lung-Kai Mao, Wen-Hsiung Lu, Pei-Wei Lee, Szu-Hsien Lee, Chieh-Ning Feng
  • Publication number: 20240096647
    Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Mirng-Ji Lii, Chen-Shien Chen, Lung-Kai Mao, Ming-Da Cheng, Wen-Hsiung Lu
  • Publication number: 20240097627
    Abstract: A class D amplifier is provided, including: a first comparator, configured to generate a first comparison result based on a positive end input signal and a triangular wave; a second comparator, configured to generate a second comparison result based on a negative end input signal and the triangular wave; an exclusive OR gate, configured to generate a first control signal based on the first comparison result and the second comparison result; a first AND gate, configured to generate a positive end PMW output based on the first comparison result and the first control signal; and a second AND gate, configured to generate a negative end PMW output based on the second comparison result and the first control signal; and an output stage, configured to generate the positive end output signal and the negative end output signal correspondingly based on the positive end PMW output and the negative end PMW output.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 21, 2024
    Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Kai MAO, Long HUANG, Junjun ZHANG, Yuqing YANG
  • Publication number: 20240073893
    Abstract: An outer loop initial value adjustment method, a device, and a readable storage medium are disclosed. The method may include: acquiring feature information of a plurality of User Equipment (UEs) scheduled by a cell; performing raster division on the feature information of the plurality of UEs to obtain a plurality of rasters; determining an outer loop corresponding to each of the rasters, where an outer loop value of each raster is within a target Block Error Rate (BLER) range; determining a target raster corresponding to a target UE according to the feature information of the target UE, where the target UE is one of the plurality of UEs scheduled by the cell; and determining the outer loop value corresponding to the target raster as an initial outer loop value of the target UE.
    Type: Application
    Filed: June 15, 2022
    Publication date: February 29, 2024
    Inventors: Ke SHI, Qiaoyan LIU, Kai MAO, Jianguo LI, Zepeng MA
  • Patent number: 11901266
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li Yang, Wen-Hsiung Lu, Lung-Kai Mao, Fu-Wei Liu, Mirng-Ji Lii