Patents by Inventor Kai Mao
Kai Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230319450Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a protrusion extending into the air gap.Type: ApplicationFiled: September 19, 2022Publication date: October 5, 2023Inventors: Chih-Yuan CHEN, Feng-Chia HSU, Chun-Kai MAO, Jien-Ming CHEN, Wen-Shan LIN, Nai-Hao KUO
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Publication number: 20230308809Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a filler structure disposed on the diaphragm, and a portion of the filler structure is disposed in the ventilation hole.Type: ApplicationFiled: August 18, 2022Publication date: September 28, 2023Inventors: Chih-Yuan CHEN, Feng-Chia HSU, Chun-Kai MAO, Jien-Ming CHEN, Wen-Shan LIN, Nai-Hao KUO
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Publication number: 20230274652Abstract: A method and a device for measuring a four-dimensional (4D) radiation pattern of an outdoor antenna based on an unmanned aerial vehicle (UAV) are provided. The device includes a measurement path planning unit, a UAV platform unit, a radiation signal acquisition unit, a data command processing unit, and a ground data processing unit. The measurement path planning unit, the radiation signal acquisition unit, and the data command processing unit each are suspended from the UAV platform unit by using a pod. The present disclosure applies to the radiation pattern measurement of an outdoor antenna.Type: ApplicationFiled: May 6, 2021Publication date: August 31, 2023Applicant: Nanjing University of Aeronautics and AstronauticsInventors: Qihui WU, Qiuming ZHU, Tianxu LAN, Yang HUANG, Jie LI, Xiaofu DU, Weizhi ZHONG, Lu HAN, Yunpeng BAI, Junjie ZHANG, Kai MAO
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Patent number: 11721579Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.Type: GrantFiled: June 30, 2022Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
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Publication number: 20230060982Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li YANG, Wen-Hsiung LU, Lung-Kai MAO, Fu-Wei LIU, Mirng-Ji LII
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Publication number: 20230034994Abstract: Provided is a channel identification method. The method includes: acquiring channel data of a terminal; constructing a first feature vector based on the channel data, where the first feature vector represents a numerical value set of cross-correlation values, which change along with time intervals, between channel data at different moments and the channel data themselves and between the channel data at different moments and subsequent channel data at different time intervals; and inputting the first feature vector into a predetermined prediction model to predict a speed of the terminal, or to predict a speed type of a cluster to which the terminal belongs. Further provided are an adaptive transmission method and apparatus based on the channel identification method, a transmission device, a base station, and a computer storage medium.Type: ApplicationFiled: December 15, 2020Publication date: February 2, 2023Inventors: Jianguo LI, Qiaoyan LIU, Kai MAO, Ting MIAO, Ke SHI
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Publication number: 20220384210Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Mirng-Ji Lii, Chen-Shien Chen, Lung-Kai Mao, Ming-Da Cheng, Wen-Hsiung Lu
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Publication number: 20220336275Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
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Publication number: 20220315066Abstract: A heat dissipation system for a high-speed train running in a low-vacuum tube is provided. Component groups that provide power and resistance for the movement and stop of a train are provided at a periphery, close to the train, in a low-vacuum tube. The component group is provided with a group A cooling assembly. The group A cooling assembly includes a group A cooling-type heat exchanger and/or a group A nozzle assembly attached to the back of the component group. Since the friction between the train running at high speed and the air in the low-vacuum tube and the operation of the key equipment in the low-vacuum tube will generate a lot of heat, the group A cooling assembly in the component group in the low-vacuum tube exchanges the heat with the air in the low-vacuum tube.Type: ApplicationFiled: February 25, 2021Publication date: October 6, 2022Applicants: HEFEI GENERAL MACHINERY RESEARCH INSTITUTE CO., LTD, HEFEI GENERAL ENVIRONMENTAL CONTROL TECHNOLOGY CO., LTD, HIWING TECHNOLOGY ACADEMY OF CASICInventors: Xiuping ZHANG, Panpan ZHAO, Junfeng WU, Ru ZHANG, Xiaoming KONG, Shuangqing XU, Dao ZHOU, Xudong YUAN, Kai MAO, Na ZHANG, Ming ZHAO, Shaowei LI, Jinglong BO
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Publication number: 20220259037Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.Type: ApplicationFiled: May 18, 2021Publication date: August 18, 2022Inventors: Jhao-Yi Wang, Chin-Yu Ku, Wen-Hsiung Lu, Lung-Kai Mao, Ming-Da Cheng
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Publication number: 20220238353Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.Type: ApplicationFiled: April 1, 2021Publication date: July 28, 2022Inventors: Mirng-Ji Lii, Chen-Shien Chen, Lung-Kai Mao, Ming-Da Cheng, Wen-Hsiung Lu
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Patent number: 11387143Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.Type: GrantFiled: October 30, 2020Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
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Publication number: 20210375674Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.Type: ApplicationFiled: October 30, 2020Publication date: December 2, 2021Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
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Patent number: 11137590Abstract: A tunable optical device including a substrate, at least one support unit, a flexible frame, an elastic component, a first reflector, and at least one actuator is provided. The support unit is fixed onto the substrate. The flexible frame is connected to the support unit and suspended above the substrate. The elastic component is connected to the flexible frame. A stiffness of the elastic component in the Z-axis is smaller than a stiffness of the flexible frame in the Z-axis. The Z-axis direction is parallel to a normal direction of the substrate. The first reflector is connected to the elastic component. The actuator is located between the flexible frame and the substrate or located between the first reflector and the substrate.Type: GrantFiled: March 11, 2016Date of Patent: October 5, 2021Assignee: Industrial Technology Research InstituteInventors: Chia-Jung Chang, Jing-Yuan Lin, Chun-Kai Mao, Jien-Ming Chen, Yu-Sheng Hsieh
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Patent number: 11120997Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.Type: GrantFiled: August 31, 2018Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chiang Chen, Chun-Hung Lee, Ryan Chia-jen Chen, Hung-Wei Lin, Lung-Kai Mao
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Publication number: 20210143662Abstract: In one example, an electronic device may include a battery, a measuring unit to record a plurality of temperature readings associated with an operation of the battery at particular time intervals, and a control unit coupled to the measuring unit. The control unit may retrieve a set of temperature readings corresponding to a period from the plurality of temperature readings, analyze the set of temperature readings corresponding to the period to determine whether a temperature of the battery exceeds a threshold, and reduce a charging voltage of the battery in response to a determination that the temperature of the battery exceeds the threshold.Type: ApplicationFiled: July 27, 2018Publication date: May 13, 2021Applicant: Hewlett-Packard Development Company, L.P.Inventors: Jen-Hao Tai, Chien-Kun Wang, Chang-Tai Lin, Xiao-Kai Mao
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Publication number: 20200075342Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.Type: ApplicationFiled: August 31, 2018Publication date: March 5, 2020Inventors: Shih-Chiang Chen, Chun-Hung Lee, Ryan Chia-jen Chen, Hung-Wei Lin, Lung-Kai Mao
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Patent number: 10284428Abstract: A graphical policy interface architecture may enable simplified graphical development of customized policy logic for software controllers to control network services, connections, and devices. The policy logic based on graphical policy logic notation may be compiled and installed at run-time into a software controller.Type: GrantFiled: June 9, 2016Date of Patent: May 7, 2019Assignee: FUJITSU LIMITEDInventors: Kai Mao, Hiroaki Komine, Takaaki Kawakami, Toshimasa Arai, Kenichi Sakurai, Minoru Takimoto
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Patent number: 10020326Abstract: A circuit protection structure applied to a gate driver that is in a display panel (GIP) is provided. The gate driver has a first metal layer, a first isolation layer, a semiconductor layer, a second metal layer, and a second isolation layer. The first metal layer, the first isolation layer, the semiconductor layer, the second metal layer, and the second isolation layer are stacked in sequence. The circuit protection structure includes a protection layer. The protection layer is located on the second isolation layer.Type: GrantFiled: April 29, 2015Date of Patent: July 10, 2018Assignee: E Ink Holdings Inc.Inventors: Kai-Mao Huang, Pei-Lin Huang, Yi-Ming Wu, Shu-Ping Yan
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Publication number: 20180130167Abstract: A client terminal starts an image capture apparatus at a first terminal device when the client terminal receives a multi-display interaction request, to capture an image at a target display interface at a second terminal device. The client terminal determines a target event and target material information correlated with the target event. The target event is displayed at the second terminal device. The client terminal provides the target material information and corresponding animation effects with the image captured by the image capture apparatus. The corresponding animation effects animate a process of the target material information leaving the display at the second terminal device and entering a display of the first terminal. The techniques of the present disclosure make the interaction process more realistic and improve user engagements.Type: ApplicationFiled: November 10, 2017Publication date: May 10, 2018Inventors: Kai Mao, Cong Shao, Yihui Liu