Patents by Inventor Kai Peter

Kai Peter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180152898
    Abstract: A remote antenna system is provided. The remote antenna system comprises an antenna controller circuit and a remote antenna circuit coupled to the antenna controller circuit by a cable. The remote antenna system further comprises a bidirectional data signal path for carrying transmit and received data signals between the antenna controller circuit and the remote antenna circuit; and a control path for carrying control information between the antenna controller circuit and the remote antenna circuit. The control path is a bidirectional control path. The control path comprises a transmit circuit comprising an input to receive control information and configured to convert the control information into a series of pulses; and a receive circuit comprising a comparator circuit configure to receive the series of pulses and reconstruct them to the control signal.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 31, 2018
    Inventors: Kai Peter Ludwig GOSSNER, Pieter LOK
  • Patent number: 9963462
    Abstract: Inhibitors of sepiapterin reductase and uses of sepiapterin reductase inhibitors in analgesia, treatment of acute and chronic pain, anti-inflammation, and immune cell regulation are disclosed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 8, 2018
    Assignee: MAX-PLANCK-GESELLSCHAFT ZUR FORDERUNG DER WISSENSCHAFTEN E.V.
    Inventors: Mark Joseph Tebbe, Holly Victoria Atton, Craig Avery, Steven Mark Bromidge, Mark Kerry, Adrian Kotei Kotey, Nathaniel J. Monck, Mirco Meniconi, Mark Peter Ridgill, Heather Tye, Eddine Saiah, Kai Peter Johnsson, Katarzyna Irena Gorska, Hairuo Peng, John Michael McCall
  • Patent number: 9952208
    Abstract: The invention relates to the field of in vitro detection methods using luminescence. Provided is a sensor molecule for detecting an analyte of interest in a sample using bioluminescence resonance energy transfer (BRET), the sensor molecule comprising a proteinaceous moiety tethered to a synthetic regulatory molecule. Also provided is an analytical device comprising a sensor and methods using the sensor molecule.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: April 24, 2018
    Assignee: Ecole Polytechnique Fédérale de Lausanne
    Inventors: Kai Peter Johnsson, Alberto Schena, Rudolf Griss
  • Publication number: 20180087083
    Abstract: The invention relates to the in vitro and in cellulo detection of the cofactors nicotinamide adenine dinucleotide (NAD) and nicotinamide adenine dinucleotide phosphate (NADP). Provided is a sensor molecule for fluorescence or luminescence-based detection of a nicotinamide adenine dinucleotide analyte, in particular for detecting the concentrations of NAD+, NADP? and/or the ratios of the concentrations of NAD?/NAD H and NADP?/NADPH, the sensor comprising (i) a binding protein (BP) for the nicotinamide adenine dinucleotide analyte, the BP being derived from sepiapterin reductase (SPR; EC 1.1.1.153) (ii) a SPR ligand (SPR-L) capable of intramolecular binding to said BP in the presence of the oxidized form of said analyte; and (iii) at least one fluorophore.
    Type: Application
    Filed: February 16, 2016
    Publication date: March 29, 2018
    Inventors: Olivier SALLIN, Luc REYMOND, Kai Peter JOHNSSON
  • Patent number: 9870258
    Abstract: Multiple scheduler verticals can allocate tasks to resources that are shared by the scheduler verticals. Information regarding a state of each resource may be stored in memory accessible by the multiple scheduler verticals, and a processor updates the information. The scheduler verticals schedule events to be performed by any of the resources, and submit updates to reflect the scheduled events in the information. In the event of conflicting events, an update corresponding to only one of the conflicting events is committed. Moreover, disruptions may be preplanned and scheduled so as to minimize impact on scheduled tasks.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: January 16, 2018
    Assignee: Google LLC
    Inventors: John Wilkes, Todd Pu-Tse Wang, Walfredo Cirne, David Oppenheimer, Brian Grant, Jason Hickey, Kai-Peter Backman, Joseph Hellerstein, David Bort
  • Publication number: 20170170596
    Abstract: A connector assembly (1) comprises an outer housing (300); and a latch (330), which is carried by the outer housing (300), to allow a coupling of the connector assembly to a corresponding counter connector. Further, the outer housing (300) is configured to receive at least one of two different types of cables (100) through a first end and at least one of two different module mating interfaces (430, 432, 434) at a second end. In another embodiment the outer housing (300) is arranged movable on an inner housing (200), and the latch (330) is rotatably arranged on the outer housing (300).
    Type: Application
    Filed: January 23, 2015
    Publication date: June 15, 2017
    Applicant: FCI Americas Technology LLC
    Inventors: Thierry Goossens, Kai Peters, Henricus E.G. Derks, Roland Tristan De Blieck
  • Publication number: 20170096435
    Abstract: Inhibitors of sepiapterin reductase and uses of sepiapterin reductase inhibitors in analgesia, treatment of acute and chronic pain, anti-inflammation, and immune cell regulation are disclosed.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 6, 2017
    Inventors: Mark Joseph Tebbe, Holly Victoria Atton, Craig Avery, Steven Mark Bromidge, Mark Kerry, Adrian Kotei Kotey, Nathaniel J. Monck, Mirco Meniconi, Mark Peter Ridgill, Heather Tye, Eddine Saiah, Kai Peter Johnsson, Katarzyna Irena Gorska, Hairuo Peng, John Michael McCall
  • Patent number: 9378051
    Abstract: Multiple scheduler verticals can allocate tasks to resources that are shared by the scheduler verticals. Information regarding a state of each resource may be stored in memory accessible by the multiple scheduler verticals, and a processor updates the information. The scheduler verticals schedule events to be performed by any of the resources, and submit updates to reflect the scheduled events in the information. In the event of conflicting events, an update corresponding to only one of the conflicting events is committed. Moreover, disruptions may be preplanned and scheduled so as to minimize impact on scheduled tasks.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: June 28, 2016
    Assignee: Google Inc.
    Inventors: John Wilkes, Todd Pu-Tse Wang, Walfredo Cirne, David Oppenheimer, Brian Grant, Jason Hickey, Kai-Peter Backman, Joseph Hellerstein, David Bort
  • Publication number: 20160146794
    Abstract: The invention relates to the field of in vitro detection methods using luminescence. Provided is a sensor molecule for detecting an analyte of interest in a sample using bioluminescence resonance energy transfer (BRET), the sensor molecule comprising a proteinaceous moiety tethered to a synthetic regulatory molecule. Also provided is an analytical device comprising a sensor and methods using the sensor molecule.
    Type: Application
    Filed: July 18, 2013
    Publication date: May 26, 2016
    Inventors: Kai Peter Johnsson, Alberto Schena, Rudolf Griss
  • Patent number: 9329892
    Abstract: Multiple scheduler verticals can allocate tasks to resources that are shared by the scheduler verticals. Information regarding a state of each resource may be stored in memory accessible by the multiple scheduler verticals, and a processor updates the information. The scheduler verticals schedule events to be performed by any of the resources, and submit updates to reflect the scheduled events in the information. In the event of conflicting events, an update corresponding to only one of the conflicting events is committed. Moreover, disruptions may be preplanned and scheduled so as to minimize impact on scheduled tasks.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: May 3, 2016
    Assignee: Google Inc.
    Inventors: John Wilkes, Todd Pu-Tse Wang, Walfredo Cirne, David Oppenheimer, Brian Grant, Jason Hickey, Kai-Peter Backman, Joseph Hellerstein, David Bort
  • Patent number: 9229774
    Abstract: Multiple scheduler verticals can allocate tasks to resources that are shared by the scheduler verticals. Information regarding a state of each resource may be stored in memory accessible by the multiple scheduler verticals, and a processor updates the information. The scheduler verticals schedule events to be performed by any of the resources, and submit updates to reflect the scheduled events in the information. In the event of conflicting events, an update corresponding to only one of the conflicting events is committed. Moreover, disruptions may be preplanned and scheduled so as to minimize impact on scheduled tasks.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: January 5, 2016
    Assignee: Google Inc.
    Inventors: John Wilkes, Todd Pu-Tse Wang, Walfredo Cirne, David Oppenheimer, Brian Grant, Jason Hickey, Kai-Peter Backman, Joseph Hellerstein, David Bort
  • Patent number: 7568180
    Abstract: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: July 28, 2009
    Assignee: PDF Solutions
    Inventors: Hans Eisenmann, Kai Peter, Dennis Ciplickas, Jonathan O. Burrows, Yunqiang Zhang Zhang
  • Publication number: 20080295061
    Abstract: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns.
    Type: Application
    Filed: February 22, 2005
    Publication date: November 27, 2008
    Inventors: Hans Eisenmann, Kai Peter, Dennis Ciplickas, Jonathan O. Burrows, Yunqiang Zhang Zhang
  • Patent number: 6926922
    Abstract: A process and composition for manufacturing printed wiring boards that reduces or eliminates the problem of depositing electroless nickel in through holes that are not designed to be metal plated is provided. Also provided by the present invention is a method and composition for depositing a final finish that is even and bright. The present invention is particularly suitable for the manufacture of printed circuit boards containing one or more electroless nickel-immersion gold layers.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: August 9, 2005
    Assignee: Shipley Company, L.L.C.
    Inventors: Mei Kiu Leung, Willetta Lai, Pit Kai Peter Cheng, Cecilia Po Sze Wong
  • Publication number: 20040022934
    Abstract: A process and composition for manufacturing printed wiring boards that reduces or eliminates the problem of depositing electroless nickel in through holes that are not designed to be metal plated is provided. Also provided by the present invention is a method and composition for depositing a final finish that is even and bright. The present invention is particularly suitable for the manufacture of printed circuit boards containing one or more electroless nickel-immersion gold layers.
    Type: Application
    Filed: April 7, 2003
    Publication date: February 5, 2004
    Applicant: Shipley Company, L.L.C.
    Inventors: Mei Kiu Leung, Willetta Lai, Pit Kai Peter Cheng, Cecilia Po Sze Wong
  • Patent number: 5930600
    Abstract: A method for bonding a component (14) to a substrate (18) via a thermally hardened or softened bonding medium, employs PTC or NTC thermistor (24) for heating the bonding medium during bonding of the component. In one disclosed example, the method is used for bonding an optical fiber to a substrate, via a solder layer (40), in alignment with a semiconductor laser (12) in a diode-laser module (10).
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: July 27, 1999
    Assignee: Coherent, Inc.
    Inventors: Wolf Seelert, Jorg Lawrenz-Stolz, Herry Wilhelm, Kai-Peter Stamer