Abstract: A full-electric drive cementing control system is disclosed.

Abstract: Methods, systems, and devices for electric machine drive calibration, verification, and efficiency improvement are disclosed herein. One electric machine controller for calibration includes a processor and memory and instructions that are stored in the memory and executable by the processor to identify a vehicle and/or electric machine frequency response during operation of the vehicle and use the electronic machine and a dynamic motor drive converter to provide source excitations based on the identified frequency response.

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.

Abstract: An iterative learning-based energy-saving control method for a piezoelectric motor, comprising: setting a sampling period of a piezoelectric motor (101); obtaining an expected output trajectory of the piezoelectric motor, and performing sampling according to the sampling period to obtain a sampled expected output sequence (102); setting an initial control input signal of the piezoelectric motor (103); obtaining an actual control input signal according to a mapping relation of the initial control input signal, and transmitting the actual control input signal to the piezoelectric motor to obtain an actual output position (104); obtaining a mapping relation of the output position of the piezoelectric motor according to the actual output position, and sampling the mapping relation according to the sampling period to obtain a sampled actual output sequence (105); calculating the difference between the sampled expected output sequence and the sampled actual output sequence to obtain a sampling error function sequen

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1 and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor. A method of forming a semiconductor device includes providing a base substrate, forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1. The method further includes forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further includes removing the base substrate.

Abstract: The invention relates to a field off artificial intelligence (AI) technologies, and discloses a method and an apparatus for high-order iterative self-learning control for a robotic fish, and a storage medium; the control method performs preferential iterative calculation on control gain elements in the control gain set to obtain a target control gain set; and performs high-order iterative calculation according to the target control gains, the first control input thrust and the first tracking error to obtain a target control input thrust, and then controls a robotic fish to swing according to the target control input thrust to obtain an expected speed. In this way, complete tracking and rapid convergence of a swim speed of a robotic fish in the whole operation space may be achieved.

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor.

Abstract: A transportation device for liquid crystal panel, wherein the transportation device comprises a housing, a bottom of the housing is provided with moving wheels, a first support portion, a second support portion, and a lifting platform supporting the second support portion. The first support portion is configured to cooperate with a first grab device, the second support portion is configured to cooperate with a second grab device.

Abstract: An electroluminescent display device and a fabricating method thereof are provided. The device has a TFT layer, a first functional layer, an electroluminescent layer, a second functional layer, and a functional bar disposed sequentially. The device uses Seebeck effect of constituent material of p-type Bi2Te3 of the functional bar to absorb heat of the TFT layer for converting the heat into electric energy, thereby effectively reducing heat of the TFT layer, reducing aging of circuit and organic material, and improving life of the electroluminescent display device. A work function of p-type Bi2Te3 material of the functional bar is 5.3 eV. An electroluminescent material has a HOMO energy level ranging from 5 to 6 eV. Under a driving of a thermoelectromotive force, majority carriers (holes) in the constituent material of p-type Bi2Te3, are injected into the electroluminescent layer to improve a carrier concentration therein, thereby improving emission luminance of the electroluminescent display device.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

Abstract: An electroluminescent display device and a fabricating method thereof are provided. The device has a TFT layer, a first functional layer, an electroluminescent layer, a second functional layer, and a functional bar disposed sequentially. The device uses Seebeck effect of constituent material of p-type Bi2Te3 of the functional bar to absorb heat of the TFT layer for converting the heat into electric energy, thereby effectively reducing heat of the TFT layer, reducing aging of circuit and organic material, and improving life of the electroluminescent display device. A work function of p-type Bi2Te3 material of the functional bar is 5.3 eV. An electroluminescent material has a HOMO energy level ranging from 5 to 6 eV. Under a driving of a thermoelectromotive force, majority carriers (holes) in the constituent material of p-type Bi2Te3, are injected into the electroluminescent layer to improve a carrier concentration therein, thereby improving emission luminance of the electroluminescent display device.

Abstract: A display panel and a display device are provided. The display panel includes a substrate, a thin film transistor layer, a light emitting device layer, a thin film encapsulation layer and a particle layer. A particle layer consisted of silver particles is disposed between the thin film transistor layer and the thin film encapsulation layer, and the density of state of photons and the spontaneous emission rate of excitons are increased so that the luminous efficiency of the OLED display panel is improved.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

Abstract: A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Abstract: A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

Abstract: An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

Abstract: An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

Abstract: A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

Abstract: A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.