Patents by Inventor Kai Wan

Kai Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040238959
    Abstract: A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Inventors: Chih-Hsiang Yao, Wen-Kai Wan, Tai-Chun Huang, Chin-Chiu Hsia
  • Publication number: 20040229460
    Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 18, 2004
    Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
  • Patent number: 6746900
    Abstract: In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: June 8, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Wen-Kai Wan, Cheng-Chung Lin, Kuei-Wu Huang, Yih-Shung Lin, Chia-Hui Lin
  • Patent number: 5946498
    Abstract: A computer system includes at least a server procedure and a client processor. The client processor includes plural applications which issue requests for execution of server procedures. A queue is present in the client processor and lists the requests. The client processor also includes plural input/output procedures which enable dispatch of requests to the server procedure. The client processor operates in conjunction with the I/O procedures, removes a request from the queue, and dispatches the request to the server procedure. The processor responds to occurrence of a time-out, with no response being received from the server procedure, to place the current request at the beginning of the queue so as to enable the I/O procedure to service a further request from the queue.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: August 31, 1999
    Assignee: International Business Machines Corporation
    Inventors: Redem Ky Chiang, Paul Kai-Wan Lee, Hai P. Nguyen, Jwu-Shyan Tarng