Abstract: A method of screening new psychoactive substance is provided, including providing a sample; placing the sample on chromatographic paper; ionizing the sample on the chromatographic paper by a direct analysis in real time (DART); performing a mass spectrometry analysis on the ionized sample to obtain a sample mass spectrum; and comparing a known standard mass spectrum with the sample mass spectrum, in which when a profile of the known standard mass spectrum is the same as a profile of the sample mass spectrum and the known standard mass spectrum is not exactly the same as the sample mass spectrum, the sample is determined to be the new psychoactive substance. A platform for screening new psychoactive substance is also provided to quickly screen out the new psychoactive substance.

Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; a gate overlying the substrate; a channel layer separated from the gate by a dielectric and overlying the gate; source/drain regions on the channel layer, the gate extending between the source/drain regions; an insertion layer conforming to an upper surface of the channel layer and comprising a first material; and a passivation layer conforming to an upper surface of the insertion layer and comprising a second material different from the first material; where the passivation layer has a higher density than the insertion layer, such that the passivation layer mitigates the diffusion of environmental materials towards the channel layer, and where the insertion layer mitigates the diffusion of the second material from the passivation layer into the channel layer.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A method for resuming topology of a single loop network and a network switch system are provided. The network switch system includes one or more first network switches each having a first port and a second port and a second network switch having a third port and a fourth port. When the first port of one of the first network switches is abnormal, a recovery control frame is transmitted through the second port. The second network switch sets the third port in a disabled state to an enabled state. When the abnormal port is resumed, the first network switch transmits a block control frame through the second port. The second network switch sets the third port in the enabled state to the disabled state and transmits a forward control frame through the fourth port. The first network switch sets the first port in the disabled state to the enabled state.

Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.

Abstract: A capacitor includes a bottom capacitor plate including a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14, a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate, and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor located on a substrate, a dielectric layer on the transistor, and a capacitor in the dielectric layer and including a bottom capacitor plate connected to a source region of the transistor and having a rough upper surface with a root mean square (RMS) surface roughness of at least 1.14.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a semiconductor substrate, a hydrogen sensing stacked layer disposed over the semiconductor substrate, and a protection layer disposed on the hydrogen sensing stacked layer. The hydrogen sensing stacked layer comprises a hydrogen-free oxide layer and a metal oxide layer disposed on the hydrogen-free oxide layer.

Abstract: Embodiments of the present disclosure provide a method including forming a gate electrode over a substrate, forming a ferroelectric layer over the gate electrode, forming a channel layer over the ferroelectric layer, forming a capping layer over the channel layer, wherein the capping layer includes one or more of CeOx, BeOx, InOx, GaOx, AlOx, SnOx, VOx, WOx, TiOx, ZrOx, NbOx, HfOx, SiOx, TaOx, a binary metal oxide based on any combination of the preceding metal oxides, or a ternary metal oxide based on any combination of the preceding metal oxides, annealing, after forming the capping layer, at a temperature less than 350° C., forming a dielectric layer over the capping layer, and forming a source contact and a drain contact in the dielectric layer.

Abstract: A method for forming a semiconductor device is provided.

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a dielectric layer, a source electrode, and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the dielectric layer is disposed on a side of the active layer, and the source electrode and the drain electrode pass through the dielectric layer to electrically connect with the active layer, wherein a first contact surface is formed between the source electrode and the active layer, a second contact surface is formed between the drain electrode and the active layer, the first contact surface and the second contact surface are subjected to a plasma treatment or a deposition treatment to form a protective interface layer.

Abstract: A semiconductor device includes a gate electrode, a gate dielectric located over the gate electrode, a channel layer including a semiconductor material and located over the gate dielectric, blocking layers located over the channel layer, covering portions of channel layer, and spaced apart from each other, buffer layers respectively located over the blocking layers, respectively surrounded by the blocking layers, and including a material that receives hydrogen, and source/drain contacts respectively located over the buffer layers and respectively surrounded by the buffer layers.

Abstract: A harness system is provided and includes an upper buckle, an upper strap and a restraining assembly. The upper strap includes shoulder portion and a waist portion divided by the upper buckle. A through slot is formed on the upper buckle. The restraining assembly includes an anti-sliding structure, a beam structure disposed on the upper buckle and a stopping component. The through slot includes a first portion and a second portion divided by the beam structure and respectively adjacent to the shoulder portion and the waist portion. The upper strap passes through the first portion of the through slot from bottom to top and passes through the second portion of the through slot from top to bottom. The stopping component is detachably disposed on the shoulder portion and configured to abut against the upper buckle for restraining a sliding movement of the upper buckle relative to the upper strap.

Abstract: A method for packet filtering in a network switch includes: utilizing an access control list circuit to filter received packets, wherein the access control list circuit compares header information of the received packets with an access control list to filter the received packets, where the access control list has at least one entry, and rule information in the entry includes only a portion of an IP address; and utilizing a routing circuit to further filter packets that pass the access control list circuit, wherein the routing circuit compares header information of the packets that pass the access control list circuit with a routing table to filter the packets, wherein the routing table has at least one entry, and rule information in the entry includes an entire IP address.

Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

Abstract: A method for resuming topology of a single loop network and a network switch system are provided. The network switch system includes one or more first network switches each having a first port and a second port and a second network switch having a third port and a fourth port. When the first port of one of the first network switches is abnormal, a recovery control frame is transmitted through the second port. The second network switch sets the third port in a disabled state to an enabled state. When the abnormal port is resumed, the first network switch transmits a block control frame through the second port. The second network switch sets the third port in the enabled state to the disabled state and transmits a forward control frame through the fourth port. The first network switch sets the first port in the disabled state to the enabled state.