Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

Abstract: A phase compensation method applied to a phase-locked loop (PLL) module of a communication device includes determining to output one of a maximum likelihood (ML) phase to an oscillator of the PLL module and a data-aided (DA) phase error to a filter of the PLL module according to an input signal. The ML phase is a phase generated from estimating known data in the input signal by using a ML method, and the DA phase error is a phase error generate from estimating the known data in the input signal by using a DA method.

Abstract: An echo cancellation circuit is provided to reduce or eliminate the effects of a pre-echo signal that is part of a received multi-path signal. The circuit includes: a delay module, receiving an input signal and delaying the input signal to generate a plurality of delayed signals; a multiplication module, multiplying the plurality of delayed signals by a plurality of coefficients to generate a plurality of multiplication results, respectively; a summing circuit, performing a summation on the plurality of multiplication results to generate a summation signal; a subtraction circuit, receiving a first delay signal and generating a subtracted signal according to the first delayed signal and the summation signal; and a coefficient calculating circuit, calculating the plurality of coefficients according to the subtracted signal. The echo cancellation circuit outputs an output signal as the subtracted signal, with the pre-echo signal diminished or eliminated.

Abstract: A manufacturing method for a car safety seat includes the following steps: providing a mold and disposing a main body of the car safety seat into the mold, and injecting a foam material into a cavity of the mold and foaming the foam material so as to form a flexible layer integrated with the main body. A pressure in the cavity is between 1.5 bar and 5.0 bar. The manufacturing method disposes the main body into the mold and directly forms a flexible layer on the main body, so that the flexible layer ensures safety and comfort of the car safety seat while saves the necessity to dispose a seat pad or a cushion and fixing structures on the main body, and thereby reduces the cost and the work-hour of assembly, and the overall weight of the car safety seat can be reduced by omitting the fixing structures.

Abstract: An electronic continuously variable transmission (ECVT) system applicable to a motorcycle includes a first speed sensor, second speed sensor, continuously variable transmission (CVT) and control unit. The control unit receives a user control signal and accordingly controls a speed-changing state of the CVT. While the motorcycle is operating in a manual-operation mode, the control unit predicts, according to the user control signal, a first speed signal sent from the first speed sensor, and a second speed signal sent from the second speed sensor, whether the next gear indicated by the shift request signal will cause the motorcycle to move unsteadily. If so, the control unit ignores the shift request signal and refuses to perform gear shifting. If not, the control unit sends at least a shift control signal to the CVT so that the CVT performs gear shifting.

Abstract: A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.

Abstract: A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.

Abstract: A phase calibration method for a phase locked loop (PLL) circuit in a wireless communication device includes: calculating a header phase error of a header sub-frame of a frame in an input signal and a pilot phase error of a pilot sub-frame of the frame, wherein the header sub-frame and the pilot sub-frame are known data; generating an estimated phase error according to a relationship between the header phase error and the pilot phase error; generating a phase compensating signal according to the estimated phase error and a filtered signal; adjusting the input signal according to the phase compensating signal to generate a compensated input signal; detecting a phase error between a data sub-frame corresponding to the pilot sub-frame in the compensated input signal and a reference signal; and generating the filtered signal according to the phase error.

Abstract: A Magnetoresistive Tunnel Junction (MTJ) device includes an elongated MTJ structure formed onto a substrate, the MTJ structure including a magnetic reference layer and a tunnel barrier layer. The MTJ device also includes a number of discrete free magnetic regions disposed onto the tunnel barrier layer. The ratio of length to width of the elongated MTJ structure is such that the magnetic field of the magnetic reference layer is pinned in a single direction.

Abstract: A bandwidth adjustment method includes obtaining an upper bandwidth limit and a lower bandwidth limit according to an initial upper bandwidth limit and an initial lower bandwidth limit, obtaining an optimum bandwidth according to the upper bandwidth limit and the lower bandwidth limit, and adjusting the initial upper bandwidth limit and the initial lower and width limit according to the optimum bandwidth.

Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

Abstract: The present disclosure illustrates a code activation device used to transmit an activation signal to a back-end device, so as to activate the back-end device. The code activation device comprises a sensing module and a processing module. The sensing module comprises a sensor unit, and the sensor unit generates sensing signals according to a preset action of a trigger object. The processing module connected to the sensing module receives the sensing signals, generates a sensing beat according to interval periods between the sensing signals, and determines whether the sensing beat matches a preset beat, wherein the processing module generates the activation signal when the sensing beat matches the preset beat.

Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.

Abstract: The present invention provides novel pyrazolo[4,3-c]quinoline derivatives exhibiting specifically inhibition activity to microbiota ?-glucuronidase, whereby providing potent activities to prevent chemotherapy-induced diarrhea (CID) of cancers. Therefore, the compounds of the present invention can be used as (1) chemotherapy-adjuvant to prevent chemotherapy-induced diarrhea (CID) and enhance chemotherapeutic efficiency of cancers; (2) health-food supplement to prevent the carcinogens induced colon carcinoma.

Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

Abstract: The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a tunneling layer disposed over the pinned layer, a free layer disposed over the tunneling layer and a capping layer disposed over the free layer. The capping layer includes metal-oxide and metal-nitride materials.

Abstract: An equalization enhancing module includes: a multiplication unit, multiplying a plurality of equalized signals by a scaling coefficient to obtain a plurality of scaled signals; a determination unit, coupled to the multiplication unit, determining whether the plurality of scaled signals are located in a predetermined region to generate a plurality of determination results; a ratio calculating unit, coupled to the determination unit, calculating an inner ratio associated with a ratio of the plurality of scaled signals located in the predetermined region; and a coefficient calculating unit, coupled to the ratio calculating unit, calculating the scaling coefficient according to the inner ratio.

Abstract: An error limiting method includes: receiving a first signal and a first error signal, wherein the first error signal is associated with the first signal and a first symbol corresponding to the first signal; calculating a first magnitude value of the first signal; and decreasing an error energy of the first error signal according to the first magnitude value of the first signal to generate a second error signal, and outputting the second error signal to an error feedback circuit.