Abstract: A filter includes a switching circuit, a first filter circuit, and a second filter circuit. The first filter circuit is coupled to the switching circuit. The second filter circuit is coupled to the switching circuit. The switching circuit is controlled to control the first filter circuit to perform a first filtering process on an input signal or control the first filter circuit to work in coordination with the second filter circuit to perform a second filtering process on the input signal.

Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.

Abstract: A successive approximation register analog-to-digital converter capable of accelerating reset comprises: a sampling circuit generating at least one output signal(s) according to at least one input signal(s); a comparator generating at least one comparator output signal(s) according to the at least one output signal(s) and a reset signal; a control circuit controlling the operation of the sampling circuit according to the at least one comparator output signal(s) or the equivalent thereof, and generating the reset signal; a first reset wire circuit outputting the reset signal to the comparator so that a first circuit of the comparator is reset when the value of the reset signal is a first value; and a second reset wire circuit outputting the reset signal to the comparator so that a second circuit of the comparator is synchronously reset when the value of the reset signal is the first value.

Abstract: The present invention discloses a resistance calibration circuit.

Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.

Abstract: A detection circuit for power over Ethernet (PoE) and a detection current generation method thereof. The detection circuit for PoE is installed in power sourcing equipment (PSE), and generates a first detection current in a first detection mode to detect a power device (PD) of a first type and generates a second detection current in a second detection mode to detect a PD of a second type. The detection circuit of PoE includes a first current source group that has at least one first current source for generating part of the first detection current in the first detection mode, and a second current source group that has multiple second current sources for generating part of the first detection current in the first detection mode and generating the second detection current in the second detection mode. The first current source group does not generate current in the second detection mode.

Abstract: The present invention discloses a voltage reference buffer circuit. An embodiment of the voltage reference buffer circuit includes: a first bias generator configured to generate a first bias voltage; a second bias generator configured to generate a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; and a second driving component coupled to the reference voltage output terminal, the second bias generator and a low voltage terminal, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage.

Abstract: The present invention discloses a resistance calibration circuit.

Abstract: A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.

Abstract: A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.

Abstract: The present invention discloses a clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit operable to generate a plurality of output clocks of the same frequency but different phases according to the reference clock and stop or start outputting the output clocks according to a power control signal; a sequential clock gating circuit operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and maintain an output cycle number relation between the gated clocks even though the multi-phase clock generating circuit stops and then starts outputting the output clocks; and a clock operation control circuit operable to provide the power control signal and the gate control signal.

Abstract: The present invention discloses a clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit operable to generate a plurality of output clocks of the same frequency but different phases according to the reference clock and stop or start outputting the output clocks according to a power control signal; a sequential clock gating circuit operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and maintain an output cycle number relation between the gated clocks even though the multi-phase clock generating circuit stops and then starts outputting the output clocks; and a clock operation control circuit operable to provide the power control signal and the gate control signal.

Abstract: The present invention provides an integrated circuit having a better ESD protection capability and capable of reducing a circuit layout area. The integrated circuit comprises: an internal circuit, a first pad, and at least a first impedance matching unit. The first impedance matching unit is coupled between the internal circuit and the first pad, and the first impedance matching unit comprises: a first switch unit and a first resistance unit. The first switch unit is coupled to the internal circuit, and the first resistance unit is coupled between the first switch unit and the first pad, wherein the first resistance unit has a first terminal and a second terminal. The first terminal is directly electrically connected to the first pad and the second terminal is coupled to the first switch unit.

Abstract: A phase calibration device comprises: an oscillator for generating a reference clock; a phase-lock-loop for generating an input clock by the reference clock; a multiphase clock generator for generating a plurality of output clocks by the input clock; a selector for selecting one of the output clocks as an operation clock; an analog-to-digital convertor for performing analog-to-digital conversion to input data by the operation clock to generate a conversion result; a control circuit for generating parameters according to the conversion result and controlling the selector to do selection; and a phase calibration circuit for outputting a calibration signal and the input clock of the phase-lock-loop to the multiphase clock generator after restarting the phase-lock-loop, so that the multiphase clock generator can correctly regenerate the output clocks by the calibration signal and the input clock, and then the control circuit controls the selector to do selection by the parameters.

Abstract: A transceiver includes a transceiver and a clock generation unit. The clock generation unit includes a clock generator, a multiplexer, and a frequency difference detector. The transceiver exchanges data with a link partner according to a first clock generated by a phase-locked loop. The clock generator is used for generating and outputting a second clock. The multiplexer is used for receiving a calibration clock or a receiver clock of the link partner, and outputting the calibration clock or the receiver clock of the link partner. The frequency difference detector is used for generating a difference signal according to a difference between the calibration clock and the second clock, or a difference between the receiver clock of the link partner and the second clock. The clock generator adjusts the shift of the second clock according to the difference signal. The phase-locked loop generates the first clock according to the second clock.

Abstract: A phase calibration device comprises: an oscillator for generating a reference clock; a phase-lock-loop for generating an input clock by the reference clock; a multiphase clock generator for generating a plurality of output clocks by the input clock; a selector for selecting one of the output clocks as an operation clock; an analog-to-digital convertor for performing analog-to-digital conversion to input data by the operation clock to generate a conversion result; a control circuit for generating parameters according to the conversion result and controlling the selector to do selection; and a phase calibration circuit for outputting a calibration signal and the input clock of the phase-lock-loop to the multiphase clock generator after restarting the phase-lock-loop, so that the multiphase clock generator can correctly regenerate the output clocks by the calibration signal and the input clock, and then the control circuit controls the selector to do selection by the parameters.

Abstract: A voltage operation system includes: a power on reset circuit, a voltage detecting circuit, an operating signal generating circuit, and an electronic fuse circuit. The power on reset circuit is used for generating a power on reset signal. The voltage detecting circuit detects an operating voltage to output a voltage detecting signal. The operating signal generating circuit, coupled to the power on reset circuit and the voltage detecting circuit-outputs an operating signal. The electronic fuse circuit can be fused according to a lock signal, a fuse signal, and the operating signal.

Abstract: A transceiver includes a transceiver and a clock generation unit. The clock generation unit includes a clock generator, a multiplexer, and a frequency difference detector. The transceiver exchanges data with a link partner according to a first clock generated by a phase-locked loop. The clock generator is used for generating and outputting a second clock. The multiplexer is used for receiving a calibration clock or a receiver clock of the link partner, and outputting the calibration clock or the receiver clock of the link partner. The frequency difference detector is used for generating a difference signal according to a difference between the calibration clock and the second clock, or a difference between the receiver clock of the link partner and the second clock. The clock generator adjusts the shift of the second clock according to the difference signal. The phase-locked loop generates the first clock according to the second clock.

Abstract: An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used for receiving a reference voltage. The electronic fuse circuit is used for changing a voltage level when a current signal passes. The first switch circuit is coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit to be disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit is for transferring the switch control signal according a control signal and a lock signal.

Abstract: The present invention provides an integrated circuit having a better ESD protection capability and capable of reducing a circuit layout area. The integrated circuit comprises: an internal circuit, a first pad, and at least a first impedance matching unit. The first impedance matching unit is coupled between the internal circuit and the first pad, and the first impedance matching unit comprises: a first switch unit and a first resistance unit. The first switch unit is coupled to the internal circuit, and the first resistance unit is coupled between the first switch unit and the first pad, wherein the first resistance unit has a first terminal and a second terminal. The first terminal is directly electrically connected to the first pad and the second terminal is coupled to the first switch unit.