Abstract: An adjustment method of moisture content and dense state for a hydrogel improved subgrade based on weather-resistance during an in-service period, including: step 1: carrying out surface cleaning and compaction of ground; step 2: preparing hydrogel improved subgrade raw material; step 3: paving the prepared material on the surface to form first-layer improved subgrade; and step 4: paving plain soil subgrade onto the first-layer. The method combines the water absorption and release function of the modified resin and the characteristic of the gel state thereof, to pave the improved subgrade in layers, which can absorb water and slightly expand when the water content in the subgrade is increased to a certain threshold value, and a strength and compactness protective layer can also be formed at the connection sections of the ground and the subgrade, and the subgrade and the pavement, to prevent the pot-cover effect from occurring.

Abstract: Disclosed is a high-precision dynamic real-time 360-degree omnidirectional point cloud acquisition method based on fringe projection. The method comprises: firstly, by means of the fringe projection technology based on a stereoscopic phase unwrapping method, and with the assistance of an adaptive dynamic depth constraint mechanism, acquiring high-precision three-dimensional (3D) data of an object in real time without any additional auxiliary fringe pattern; and then, after a two-dimensional (2D) matching points optimized by the means of corresponding 3D information is rapidly acquired, by means of a two-thread parallel mechanism, carrying out coarse registration based on Simultaneous Localization and Mapping (SLAM) technology and fine registration based on Iterative Closest Point (ICP) technology.

Abstract: A method of managing a resource is provided, including: creating, in response to an operation of a user joining in a proprietary cloud platform, a shadow account for the user on the proprietary cloud platform; determining a resource pool corresponding to the shadow account; and accessing, in response to the user accessing the proprietary cloud platform, a resource in the resource pool corresponding to the shadow account based on a preset access policy. An apparatus of managing a resource, a computer system, and a computer-readable storage medium are further provided.

Abstract: The present disclosure teaches a Field-Effect Transistor (FET) configured as a diode to provide ESD protection. The field-effect transistor has its gate, source, and body connected to a common power supply rail. A low-density doped drain region extends in a length direction beyond the gate sidewall spacers of the transistor to provide a lower leakage current than would otherwise be exhibited by the protection device.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate, a body region disposed in the semiconductor substrate within the doped isolation barrier and in which a channel is formed during operation, an isolation contact disposed at the semiconductor substrate and to which a voltage is applied during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate, the plurality of reduced surface field (RESURF) layers being arranged in a stack between the body region and the isolation contact.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate, a body region disposed in the semiconductor substrate within the doped isolation barrier and in which a channel is formed during operation, an isolation contact disposed at the semiconductor substrate and to which a voltage is applied during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate, the plurality of reduced surface field (RESURF) layers being arranged in a stack between the body region and the isolation contact.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate within the doped isolation barrier, having the first conductivity type, and in which a channel is formed during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate. The plurality of RESURF layers are arranged in a stack between the body region and the doped isolation barrier. The plurality of RESURF layers include an upper layer having a second conductivity type, a lower layer having the second conductivity type, and an isolation coupling layer disposed between the upper and lower layers, in contact with the doped isolation barrier, and having the first conductivity type.

Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.

Abstract: Laterally diffused metal-oxide-semiconductor (LDMOS) device is disclosed. The device is surrounded by an isolation ring and a buried layer of a first doping type, that is of the same type as its source and drain regions of the same doping type. A control gate of the device includes step gate dielectric.

Abstract: A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.

Abstract: A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.

Abstract: A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.

Abstract: A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a composite source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, and a gate structure supported by the semiconductor substrate and having a side adjacent the composite source region. The composite source region includes a plurality of first constituent source regions disposed along the side of the gate structure and having the second conductivity type, and a second constituent source region disposed along the side of the gate structure and between two first constituent source regions of the plurality of first constituent source regions, the second constituent source region having the second conductivity type. The second constituent source region has a different dopant concentration level than the plurality of first constituent source regions.

Abstract: A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the drain region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the drain region.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

Abstract: A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the drain region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the drain region.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.