Abstract: The embodiments described herein provide an antifuse that includes a substrate material and an isolation trench formed in the substrate material, where the isolation trench has a first side and a second side opposite the first side. An electrode is positioned above the substrate material and proximate to the first side of the isolation trench. An insulating layer is disposed between the electrode and the substrate material. So configured, a voltage or current applied between the electrode and the substrate material causes a rupture in the insulating layer and creates a current path through the insulating layer and under the isolation trench to the substrate material proximate the second side of the isolation trench.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Abstract: An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.

Abstract: A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.

Abstract: A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions.

Abstract: Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.

Abstract: Methods are provided for forming a device that includes merged vertical and lateral transistors with collector regions of a first conductivity type between upper and lower base regions of opposite conductivity type that are Ohmically coupled via intermediate regions of the same conductivity type and to the base contact. The emitter is provided in the upper base region and the collector contact is provided in outlying sinker regions extending to the thin collector regions and an underlying buried layer. As the collector voltage increases part of the thin collector regions become depleted of carriers from the top by the upper and from the bottom by the lower base regions. This clamps the collector regions' voltage well below the breakdown voltage of the PN junction formed between the buried layer and the lower base region. The gain and Early Voltage are increased and decoupled and a higher breakdown voltage is obtained.

Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are provided. In one embodiment, the method includes the step or process of providing a substrate having therein a semiconductor base region of a first conductivity type and first doping density proximate an upper substrate surface. A multilevel collector structure of a second opposite conductivity type is formed in the base region. The multilevel collector includes a first collector part extending to a collector contact, a second collector part Ohmically coupled to the first collector part underlying the upper substrate surface by a first depth, a third collector part laterally spaced apart from the second collector part and underlying the upper substrate surface by a second depth and having a first vertical thickness, and a fourth collector part Ohmically coupling the second and third collector parts and having a second vertical thickness different than the first vertical thickness.

Abstract: Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

Abstract: A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type.

Abstract: Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.