Abstract: A process for forming a buried patterned silicon oxide layer in a silicon chip in which the layer is formed by implanting oxygen into the chip through a mask of silicon oxide on the surface of the silicon chip. The silicon oxide mask is formed to have essentially vertical side walls by interposing an irradiation step between a pair of isotropic wet etching steps in its formation.

Abstract: A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs.

Abstract: A vertical j-MOSFET useful as a power transistor includes a two-dimensional array of square cells in which a small fraction of the cells are replaced by a double-junction sink useful for collecting the minority carriers in the channel regions that normally will accumulate at each interface of the gate electrode and channel region.

Abstract: A method is provided for selectively etching ion-implanted silicon dioxide. A masked silicon dioxide layer is exposed to an ion beam of controlled dose and energy. The mask is removed and the silicon dioxide layer is brought in contact with an aqueous ammoniacal hydrogen peroxide solution which preferentially removes the ion-bombarded region with minimal etching of the unimplanted silicon dioxide.