Abstract: A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.

Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

Abstract: A light source module includes a first light-emitting unit, a second light-emitting unit, a first dichroic mirror, and a wavelength conversion unit. The first light-emitting unit emits a first color light. The second light-emitting unit emits a second color light. The first dichroic mirror allows the first color light to transmit through and has a passing area. The passing area allows the second color light to pass through. The wavelength conversion unit includes a substrate and a phosphor layer disposed on the substrate. The phosphor layer converts the first color light transmitting through the first dichroic mirror into a third color light, and reflects and scatters the second color light passing through the passing area. The first dichroic mirror reflects the second color light reflected by the wavelength conversion unit and the third color light.

Abstract: A light source module includes a first light-emitting unit, a second light-emitting unit, a first dichroic mirror, and a wavelength conversion unit. The first light-emitting unit emits a first color light. The second light-emitting unit emits a second color light. The first dichroic mirror allows the first color light to transmit through and has a passing area. The passing area allows the second color light to pass through. The wavelength conversion unit includes a substrate and a phosphor layer disposed on the substrate. The phosphor layer converts the first color light transmitting through the first dichroic mirror into a third color light, and reflects and scatters the second color light passing through the passing area. The first dichroic mirror reflects the second color light reflected by the wavelength conversion unit and the third color light.

Abstract: A light source module includes a solid-state light emitter, a reflective mirror, a light integration box, and a light sensor. The solid-state light emitter is configured to emit light. The reflective mirror is configured to turn a first part of the light and allow a second part of the light to pass. The light integration box is disposed in a path of the second part of the light and has an entrance. The second part of the light passes through the entrance to enter into the light integration box and is uniformly mixed in the light integration box. The light sensor is disposed on the light integration box to receive the second part of the light.

Abstract: A light source module includes a solid-state light emitter, a reflective mirror, a light integration box, and a light sensor. The solid-state light emitter is configured to emit light. The reflective mirror is configured to turn a first part of the light and allow a second part of the light to pass. The light integration box is disposed in a path of the second part of the light and has an entrance. The second part of the light passes through the entrance to enter into the light integration box and is uniformly mixed in the light integration box. The light sensor is disposed on the light integration box to receive the second part of the light.

Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

Abstract: A method includes operation below: extracting layout patterns that include interconnection layers between a first terminal and a second terminal coupled to the first terminal, in a layout design of a circuit; comparing a first portion of the layout patterns with a first coding portion that specifies a first layout constraint, in which the first portion of the layout patterns is extracted in a sequence starting from the first terminal or to the first terminal; comparing a second portion of the layout patterns with a second coding portion that specifies a second layout constraint, in which the second portion of the layout patterns is extracted in a sequence from the second terminal or to the second terminal; in response to comparisons, initiating fabrication of at least one element of the circuit according to the layout design.

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.

Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.

Abstract: A method includes operation below: extracting layout patterns that include interconnection layers between a first terminal and a second terminal coupled to the first terminal, in a layout design of a circuit; comparing a first portion of the layout patterns with a first coding portion that specifies a first layout constraint, in which the first portion of the layout patterns is extracted in a sequence starting from the first terminal or to the first terminal; comparing a second portion of the layout patterns with a second coding portion that specifies a second layout constraint, in which the second portion of the layout patterns is extracted in a sequence from the second terminal or to the second terminal; in response to comparisons, initiating fabrication of at least one element of the circuit according to the layout design.

Abstract: A projection system is provided, which includes a first light source, a second light source, a wavelength converter, a first light splitting element, and a second light splitting element. The first light source is configured to emit a first light. The second light source is configured to emit a second light. The wavelength converter is configured to convert portions or all of the second light into a third light. The third light includes a red light and a green light. A wavelength range of the first light is within a wavelength range of the red light. The first light splitting element is configured to permit the first light to pass through or to be reflected. The second light splitting element is configured for removing a portion of the first light or not removing the first light.

Abstract: A method includes operation below. At least one portion of layout patterns coupled between a first terminal and a second terminal of a circuit is extracted from a layout design for the circuit. The at least one portion is compared with at least one coding portion, in which the at least one coding portion specifies layout constraints for either the first terminal or the second terminal of the circuit. When the at least one portion meets the at least one coding portion, fabrication of the circuit is initiated according to the layout design.

Abstract: A projection system is provided, which includes a first light source, a second light source, a wavelength converter, a first light splitting element, and a second light splitting element. The first light source is configured to emit a first light. The second light source is configured to emit a second light. The wavelength converter is configured to convert portions or all of the second light into a third light. The third light includes a red light and a green light. A wavelength range of the first light is within a wavelength range of the red light. The first light splitting element is configured to permit the first light to pass through or to be reflected. The second light splitting element is configured for removing a portion of the first light or not removing the first light.

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.

Abstract: A method includes operation below. At least one portion of layout patterns coupled between a first terminal and a second terminal of a circuit is extracted from a layout design for the circuit. The at least one portion is compared with at least one coding portion, in which the at least one coding portion specifies layout constraints for either the first terminal or the second terminal of the circuit. When the at least one portion meets the at least one coding portion, fabrication of the circuit is initiated according to the layout design.

Abstract: A method includes the operation below. Groups, indicating layout patterns of interconnection layers, are assigned to a circuit, to determine layout constraints of the circuit. Layout patterns are extracted from a layout design for the circuit. The layout patterns are compared with the layout constraints. Data, indicating the layout design, for fabrication of the circuit are generated in a condition that the layout patterns meet the layout constraints.