Abstract: A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.

Abstract: A method of etching an article having a substrate, an etchable film and a mask layer having a pattern formed therein includes the step of exposing the article to an etchant gas mixture which includes a halogen-containing gas and an inert gas. An etching profile is formed which is substantially smooth across an interface between the etchable film and the mask layer. The method is particularly useful in producing components of articles such as flat-panel displays.

Abstract: A method for protecting a selected area of a substrate against deposition on the selected area. The method includes the steps of flowing a process gas into a substrate processing chamber and flowing a purge gas to the selected area of the substrate to prevent the process gas from contacting the selected area or minimize contact between the process gas and the selected area. In various embodiments the selected area is a backside periphery of the substrate or the edge of the substrate. Also in these embodiments, the process gas is flowed into a deposition zone in order to deposit a thin film layer over an upper surface of the substrate, and a flow of the process and purge gas is established such that the process gas flows radically across the upper surface of the substrate, combines with the purge gas near an edge of the substrate and exits the processing chamber through an exhaust system.

Abstract: An RIE method and apparatus for etching through the material layer of a transparent-electrode (ITO) in a single continuous step at a rate better than 100 .ANG./min and with a selectivity better than 20 to 1 is disclosed. Chamber pressure is maintained at least as low as 60 mTorr. A reactive gas that includes ethyl iodide C.sub.2 H.sub.5 I) is used alone or in combination with another gas such as O.sub.2. Plasma-induced light emissions of reaction products and/or the reactants are monitored to determine the time point of effective etch-through.

Abstract: A method for cleaning a deposition chamber that is used in fabricating electronic devices including the steps of delivering a precursor gas into a remote chamber that is outside of the deposition chamber, activating the precursor gas in the remote chamber via a high power source to form a reactive species, flowing the reactive species from the remote chamber into the deposition chamber, and using the reactive species that is flowed into the deposition chamber from the remote chamber to clean the inside of the deposition chamber.

Abstract: A substrate processing reactor capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and other substrate processing operations all of which can either be performed separately or as part of in-situ multiple step processing. The reactor incorporates a uniform radial gas pumping system which enables uniform reactant gas flow across the wafer. Also included are upper and lower purge gas dispersers. The upper purge gas disperser directs purge gas flow downwardly toward the periphery of the wafer while the lower gas disperser directs purge gas across the backside of the wafer. The radial pumping gas system and purge gas dispersers sweep radially away from the wafer to prevent deposition external to the wafer and keep the chamber clean.

Abstract: A chamber for processing substrates includes a support member therein which is suspended from a sidewall of the chamber. The support member includes multiple planar faces for receiving substrates thereon, and is rotatable about a horizontal axis to position the multiple planar faces in a horizontal position to place the substrates on the planar faces or remove the substrates from the planar faces, and a second position to place the substrates in a non-horizontal position for processing. A clamping and lifting apparatus is provided on the support member. The clamping and lifting apparatus is positionable, with respect to the support member, in an extended position to permit a substrate to be positioned between the clamping and lifting assembly and the support member, and in a retracted position to clamp the substrate to the support member. A clamp actuator is disposed on the chamber wall to move the clamping and lifting assembly between the extended and retracted positions.

Abstract: A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.

Abstract: An RIE method and apparatus for etching through the material layer of a transparent-electrode (ITO) in a single continuous step at a rate better than 80 .ANG./min is disclosed. Chamber pressure is maintained at least as low as 30 mTorr. A reactive gas that includes a halogen hydride such as HCl is used alone or in combination with another reactive gas such as Cl.sub.2. Plasma-induced light emissions of reaction products and/or the reactants are monitored to determine the time point of effective etch-through.

Abstract: A multi-step CVD method for thin film transistor is disclosed. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

Abstract: An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer.

Abstract: High quality silicon nitride thin films can be deposited by plasma CVD onto large area glass substrates at high deposition rates by adjusting the spacing between the gas inlet manifold and substrate, maintaining the temperature at about 300.degree.-350.degree. C., and a pressure of at least 0.8 Torr. Subsequently deposited different thin films can also be deposited in separate chemical vapor deposition chambers which are part of a single vacuum system.

Abstract: An apparatus and method for protecting conductive, typically metallic, walls (212) of a plasma process chamber (200) from accumulation of contaminants thereon and from reaction with a gas plasma and either deposition-gas plasma by-products. A ceramic barrier material (220-223), preferably of at least 0.005 inches 127 micrometers) thickness, is used adjacent the conductive portions of the reactor chamber and between the gas plasma and such conductive portions to be protected. The ceramic barrier material reduces the deposit of compounds formed from the plasma on protected reactor chamber surfaces and thereby avoiding the formation of a source of particulates. Further, the ceramic barrier material enables cleaning of the reactor chamber using an etch plasma generated from halogen-comprising gas without the etch plasma attacking protected metallic portions of the reactor.

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer.

Abstract: A high pressure, high throughout, single wafer semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature process for forming a highly conformal layer of silicon dioxide from a plasma of TEOS, oxygen and ozone is also disclosed. This layer can be planarized using an etchback process. Silicon oxide deposition and etchback can be carried out sequentially in the reactor.

Abstract: A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer if insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Abstract: A planarizing process for planarizing an integrated circuit structure in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises flowing white depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus.

Abstract: A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer.

Abstract: A process for cleaning a reactor chamber both locally adjacent the RF electrodes and also throughout the chamber and the exhaust system to the including components such as the throttle valve. Preferably, a two-step continuous etch sequence is used in which the first step uses relatively high pressure, close electrode spacing and fluorocarbon gas chemistry for etching the electodes locally and the second step uses relatively lower pressure, farther electrode spacing and fluorinated gas chemistry for etching throughout the chamber and exhaust system. The local and extended etch steps may be used separately as well as together.