Patents by Inventor Kamal K. Sikka
Kamal K. Sikka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7928562Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.Type: GrantFiled: July 22, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Amilcar R. Arvelo, Evan G. Colgan, John H. Magerlein, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jeffrey A. Zitz
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Patent number: 7875972Abstract: Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE1, the buffer layer has a second CTE, CTE2, and the semiconductor device has a third CTE, CTE3, wherein CTE1>CTE2>CTE3.Type: GrantFiled: June 25, 2009Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Virendra R. Jadhav, Kamal K. Sikka, Jiantao Zheng
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Publication number: 20100327430Abstract: Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE1, the buffer layer has a second CTE, CTE2, and the semiconductor device has a third CTE, CTE3, wherein CTE1>CTE2>CTE3.Type: ApplicationFiled: June 25, 2009Publication date: December 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Virendra R. Jadhav, Kamal K. Sikka, Jiantao Zheng
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Patent number: 7812438Abstract: The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.Type: GrantFiled: January 7, 2008Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Virendra R. Jadhav, David L. Questad, Kamal K. Sikka, Xiaojin Wei, Jiantao Zheng
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Patent number: 7768121Abstract: Apparatus and methods are provided for thermally coupling a semiconductor chip directly to a heat conducting device (e.g., a copper heat sink) using a thermal joint that provides increased thermal conductivity between the heat conducting device and high power density regions of the semiconductor chip, while minimizing or eliminating mechanical stress due to the relative displacement due to the difference in thermal expansion between the semiconductor chip and the heat conducting device.Type: GrantFiled: October 29, 2007Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Evan George Colgan, Jeffrey D. Gelorme, Kamal K. Sikka, Hilton T. Toy, Jeffrey Allen Zitz
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Patent number: 7733655Abstract: A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive.Type: GrantFiled: July 22, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Martin Beaumier, Mohamed Belazzouz, Peter J Brofman, David L Edwards, Kamal K Sikka, Jiantao Zheng, Jeffrey A Zitz
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Publication number: 20100020503Abstract: A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MARTIN BEAUMIER, MOHAMED BELAZZOUZ, PETER J. BROFMAN, DAVID L. EDWARDS, KAMAL K. SIKKA, JIANTAO ZHENG, JEFFREY A. ZITZ
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Publication number: 20100019377Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Applicant: International Business Machines CorporationInventors: Amilcar R. Arvelo, Evan G. Colgan, John H. Magerlein, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jeffrey A. Zitz
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Publication number: 20090174084Abstract: The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.Type: ApplicationFiled: January 7, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Virendra R. Jadhav, David L. Questad, Kamal K. Sikka, Xiaojin Wei, Jiantao Zheng
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Publication number: 20090098666Abstract: Methods of assembling a chip package are disclosed that employ heat from test pattern operation of the chip to cure a thermal interface material. The methods may also simultaneously verify thermal performance of the package using the heat from test pattern operation. Further, the heat may be used to cure the sealing material and/or underfill material, where they are used.Type: ApplicationFiled: October 11, 2007Publication date: April 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald L. Hering, Kathryn C. Rivera, Kamal K. Sikka
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Publication number: 20090095444Abstract: Low-pressure drop thermal assemblies, systems and methods of making low-pressure drop thermal assemblies for use in high power flux situations. A manifold body is attached to a distributor to form a subassembly. This subassembly is in communication with a substrate surface, which has a semiconductor device in need of thermal management thereon. An enclosed cavity is formed between the target substrate surface and the subassembly, and a seal of the cavity protects critical components residing on the active surface of the semiconductor device. The distributor includes a distributed liquid impingement microjet inlet array isolated from and parallel with a distributed microjet drain array for impinging cooling fluid and removing spent heated fluid in a direction orthogonal to a target surface for maximizing the heat transfer rate, and thereby providing high cooling flux capabilities while enabling low-pressure drops.Type: ApplicationFiled: December 18, 2008Publication date: April 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raschid J. Bezama, Govindarajan Natarajan, Kamal K. Sikka, Hilton T. Toy
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Patent number: 7516776Abstract: Low-pressure drop thermal assemblies, systems and methods of making low-pressure drop thermal assemblies for use in high power flux situations. A manifold body is attached to a distributor to form a subassembly. This subassembly is in communication with a substrate surface, which has a semiconductor device in need of thermal management thereon. An enclosed cavity is formed between the target substrate surface and the subassembly, and a seal of the cavity protects critical components residing on the active surface of the semiconductor device. The distributor includes a distributed liquid impingement microjet inlet array isolated from and parallel with a distributed microjet drain array for impinging cooling fluid and removing spent heated fluid in a direction orthogonal to a target surface for maximizing the heat transfer rate, and thereby providing high cooling flux capabilities while enabling low-pressure drops.Type: GrantFiled: May 19, 2005Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: Raschid J. Bezama, Govindarajan Natarajan, Kamal K. Sikka, Hilton T. Toy
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Patent number: 7489512Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.Type: GrantFiled: June 5, 2007Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Jeffrey T. Coffin, Michael A. Gaynes, David L. Questad, Kamal K. Sikka, Hilton T. Toy, Jamil A. Wakil
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Publication number: 20080303021Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.Type: ApplicationFiled: May 7, 2008Publication date: December 11, 2008Applicant: International Business Machines CorporationInventors: Jeffrey T. Coffin, Michael A. Gaynes, David L. Questad, Kamal K. Sikka, Hilton T. Toy, Jamil A. Wakil
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Patent number: 7319591Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.Type: GrantFiled: May 26, 2005Date of Patent: January 15, 2008Assignee: International Business Machines CorporationInventors: Jeffrey T. Coffin, Michael A. Gaynes, David L. Questad, Kamal K. Sikka, Hilton T. Toy, Jamil A. Wakil
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Patent number: 7288839Abstract: Apparatus and methods are provided for thermally coupling a semiconductor chip directly to a heat conducting device (e.g., a copper heat sink) using a thermal joint that provides increased thermal conductivity between the heat conducting device and high power density regions of the semiconductor chip, while minimizing or eliminating mechanical stress due to the relative displacement due to the difference in thermal expansion between the semiconductor chip and the heat conducting device.Type: GrantFiled: February 27, 2004Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Evan George Colgan, Jeffrey D. Gelorme, Kamal K. Sikka, Hilton T. Toy, Jeffrey Allen Zitz
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Patent number: 7250576Abstract: A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.Type: GrantFiled: May 19, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Evan G. Colgan, David L. Edwards, Benjamin V. Fasano, Kamal K. Sikka, Jeffrey A. Zitz, Wei Zou
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Patent number: 6292367Abstract: A heat sink assembly and process for fabricating the assembly in which a semiconductor chip is formed with at least one high conductivity layer on its back side and some of the integrated circuits are high power circuits and, during operation, generate “hot spots” of high temperature but, due to the presence of the high conductivity layer, the “hot spots” are dissipated and the maximum chip temperature is lowered to create a uniform and lower temperature across the chip.Type: GrantFiled: June 22, 2000Date of Patent: September 18, 2001Assignee: International Business Machines CorporationInventors: Kamal K. Sikka, John U. Knickerbocker, Subhash L. Shinde