Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive blocks are formed over a construction. Each of the conductive blocks is over a set which includes a pair of storage-element-contact-regions and a digit-line-contact-region. Each of the conductive blocks is entirely laterally surrounded by first insulative material. Central regions of the conductive blocks are removed to split each of the conductive blocks into a first conductive portion over one of the storage-element-contact-regions and a second conductive portion over another of the storage-element-contact-regions. Second insulative material is formed between the first and second conductive portions. Digit-lines are coupled with the digit-line-contact-regions, and storage-elements are coupled with the storage-element-contact-regions.

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive blocks are formed over a construction. Each of the conductive blocks is over a set which includes a pair of storage-element-contact-regions and a digit-line-contact-region. Each of the conductive blocks is entirely laterally surrounded by first insulative material. Central regions of the conductive blocks are removed to split each of the conductive blocks into a first conductive portion over one of the storage-element-contact-regions and a second conductive portion over another of the storage-element-contact-regions. Second insulative material is formed between the first and second conductive portions. Digit-lines are coupled with the digit-line-contact-regions, and storage-elements are coupled with the storage-element-contact-regions.

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

Abstract: Some embodiments include an integrated assembly having a ferroelectric transistor body region between a first comparative digit line and a second comparative digit line. A carrier-reservoir structure is coupled with the ferroelectric transistor body region through an extension that passes along a side of the first comparative digit line. Some embodiments include an integrated assembly having a conductive structure over a carrier-reservoir structure. A bottom of the conductive structure is spaced from the carrier-reservoir structure by an insulative region. A ferroelectric transistor is over the conductive structure. The ferroelectric transistor has a bottom source/drain region over the conductive structure, has a body region over the bottom source/drain region, and has a top source/drain region over the body region. An extension extends upwardly from the carrier-reservoir structure, along a side of the conductive structure, and to a bottom of the body region.

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions.

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions.

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions.

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

Abstract: Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.