Patents by Inventor Kamal M. Karda

Kamal M. Karda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field effect transistor constructions with gate insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to a channel core periphery
    Patent number: 11170835
    Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Durai Vishak Nirmal Ramaswamy, F. Daniel Gealy
  • Channel conduction in semiconductor devices
    Patent number: 11171206
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Integrated assemblies having ferroelectric transistors with heterostructure active regions
    Patent number: 11164889
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Devices including vertical transistors, and related methods
    Patent number: 11139396
    Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Transistors including two-dimensional materials
    Patent number: 11127747
    Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Akira Goda, Sanh D. Tang, Gurtej S. Sandhu, Litao Yang, Haitao Liu
  • Integrated assemblies comprising hydrogen diffused within two or more different semiconductor materials, and methods of forming integrated assemblies
    Patent number: 11107817
    Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Yi Fang Lee, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi, Karthik Sarpatwari, Scott E. Sills, Sameer Chhajed
  • Integrated Assemblies Having Polycrystalline First Semiconductor Material Adjacent Conductively-Doped Second Semiconductor Material
    Publication number: 20210265467
    Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Deepak Chandra Pandey, Haitao Liu, Richard J. Hill, Guangyu Huang, Yunfei Gao, Ramanathan Gandhi, Scott E. Sills
  • DEVICES AND SYSTEMS WITH STRING DRIVERS INCLUDING HIGH BAND GAP MATERIAL AND METHODS OF FORMATION
    Publication number: 20210265499
    Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Inventors: Haitao Liu, Guangyu Huang, Chandra V. Mouli, Akira Goda, Deepak Chandra Pandey, Kamal M. Karda
  • Integrated Assemblies Having Ferroelectric Transistors with Heterostructure Active Regions
    Publication number: 20210242221
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Single word line gain cell with complementary read write channel
    Patent number: 11043260
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Programmable Charge-Storage Transistor, An Array Of Elevationally-Extending Strings Of Memory Cells, And A Method Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells
    Publication number: 20210184044
    Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 17, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Haitao Liu, Kamal M. Karda, Albert Fayrushin
  • SEMICONDUCTOR DEVICES, HYBRID TRANSISTORS, AND RELATED METHODS
    Publication number: 20210183951
    Abstract: Methods of forming a semiconductor device are disclosed. A method comprising forming a hybrid transistor supported by a substrate. Forming the hybrid transistor comprises forming a source including a first low bandgap high mobility material, and forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material. Forming the hybrid transistor further comprises forming a drain including a second low bandgap high mobility material coupled with the a high bandgap low mobility material, and forming a gate separated from the channel via a gate oxide material. Methods of forming a transistor are also disclosed.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 17, 2021
    Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy
  • Integrated assemblies having polycrystalline first semiconductor material adjacent conductively-doped second semiconductor material
    Patent number: 11038027
    Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Deepak Chandra Pandey, Haitao Liu, Richard J. Hill, Guangyu Huang, Yunfei Gao, Ramanathan Gandhi, Scott E. Sills
  • Devices and systems with string drivers including high band gap material and methods of formation
    Patent number: 11018255
    Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Guangyu Huang, Chandra V. Mouli, Akira Goda, Deepak Chandra Pandey, Kamal M. Karda
  • MICROELECTRONIC DEVICES INCLUDING PASSIVATION MATERIALS, RELATED ELECTRONIC DEVICES, AND RELATED METHODS
    Publication number: 20210143284
    Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Inventors: Kamal M. Karda, Haitao Liu
  • DRIVER PLACEMENT IN MEMORIES HAVING STACKED MEMORY ARRAYS
    Publication number: 20210134825
    Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 6, 2021
    Inventors: Haitao Liu, Kamal M. Karda, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu
  • Integrated assemblies having ferroelectric transistors with heterostructure active regions
    Patent number: 10998338
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Device including a vertical transistor having a large band gap channel material and void spaces adjacent gate electrodes, and related methods and systems
    Patent number: 10998440
    Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Ramanathan Gandhi, Hong Li, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Sanh D. Tang, Scott E. Sills
  • Semiconductor devices, hybrid transistors, and related methods
    Patent number: 10943953
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a hybrid transistor including a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material. Memory arrays, semiconductor devices, and systems incorporating memory cells, and hybrid transistors are also disclosed, as well as related methods for forming and operating such devices.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy
  • Integrated memory having the body region comprising a different semiconductor composition than the source/drain region
    Patent number: 10943915
    Abstract: Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Albert Fayrushin, Haitao Liu, Kirk D. Prall