Patents by Inventor Kamalesh K. Srivastava

Kamalesh K. Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11244917
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11171102
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11094657
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190326243
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190326242
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 10403590
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 10396051
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190157230
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20170170135
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20170133338
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 11, 2017
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9640501
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9472520
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9111816
    Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: August 18, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20150054152
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 26, 2015
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Additives for grain fragmentation in Pb-free Sn-based solder
    Patent number: 8910853
    Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham, Hsichang Liu, Eric D. Perfecto, Srinivasa S.N. Reddy, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof, Julien Sylvestre, Renee L. Weisman
  • ADDITIVES FOR GRAIN FRAGMENTATION IN Pb-FREE Sn-BASED SOLDER
    Publication number: 20130284495
    Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
    Type: Application
    Filed: July 1, 2013
    Publication date: October 31, 2013
    Inventors: Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham, Hsichang Liu, Eric D. Perfecto, Srinivasa S.N. Reddy, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof, Julien Sylvestre, Renee L. Weisman
  • Additives for grain fragmentation in Pb-free Sn-based solder
    Patent number: 8493746
    Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham, Hsichang Liu, Eric D. Perfecto, Srinivasa S. N. Reddy, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof, Julien Sylvestre, Renee L. Weisman
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20120312447
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers
    Patent number: 8314500
    Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 20, 2012
    Assignee: Ultratech, Inc.
    Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K Srivastava, Michael J. Sullivan
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 8293587
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Virendra R Jadhav, Krystyna W Semkow, Kamalesh K Srivastava, Brian R Sundlof