Patents by Inventor Kamalesh K. Srivastava
Kamalesh K. Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120181071Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
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Patent number: 8197612Abstract: Semiconductor packaging techniques are provided which optimize metallurgical properties of a joint using dissimilar solders. A solder composition for Controlled Collapse Chip Connection processing includes a combination of a tin based lead free solder component designed for a chip and a second solder component designed for a laminate. The total concentration of module Ag after reflow is less than 1.9% by weight. A method of manufacturing a solder component is also provided.Type: GrantFiled: April 29, 2008Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: James A Busby, Minhua Lu, Valerie A Oberson, Eric D Perfecto, Kamalesh K Srivastava, Brian R Sundlof, Julien Sylvestre, Renee L Weisman
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Publication number: 20120083113Abstract: A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: International Business Machines CorporationInventors: Charles L. Arvin, Valerie Oberson, Srinivasa N. Reddy, Krystyna W. Semkow, Richard A. Shelleman, Kamalesh K. Srivastava
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Publication number: 20110195543Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.Type: ApplicationFiled: April 21, 2011Publication date: August 11, 2011Applicant: International Business Machines CorporationInventors: Virendra R. Jadhav, Jayshree Shah, Kamalesh K. Srivastava
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Patent number: 7952207Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.Type: GrantFiled: December 5, 2007Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Virendra R. Jadhav, Jayshree Shah, Kamalesh K. Srivastava
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Patent number: 7932169Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.Type: GrantFiled: October 5, 2009Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K Srivastava, Michael J. Sullivan
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Patent number: 7784669Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: GrantFiled: August 5, 2009Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Gareth G. Hougham, Kamalesh K. Srivastava, Sung K. Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey, Donald W. Henderson, David R. Di Milia, Richard P. Ferlita, Roy A. Carruthers
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Publication number: 20100200271Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.Type: ApplicationFiled: February 12, 2010Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham, Hsichang Liu, Eric D. Perfecto, Srinivasa S.N. Reddy, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof, Julien Sylvestre, Renee L. Weisman
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Patent number: 7767575Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.Type: GrantFiled: January 2, 2009Date of Patent: August 3, 2010Assignee: Tessera Intellectual Properties, Inc.Inventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quinn, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Publication number: 20100155456Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: ApplicationFiled: August 5, 2009Publication date: June 24, 2010Applicant: International Business Machines Corp.Inventors: GARETH G. HOUGHAM, KAMALESH K. SRIVASTAVA, SUNG K. KANG, DA-YUAN SHIH, BRIAN R. SUNDLOF, S. JAY CHEY, DONALD W. HENDERSON, DAVID R. DI MILIA, RICHARD P. FERLITA, ROY A. CARRUTHERS
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Patent number: 7703661Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduced or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: GrantFiled: May 23, 2007Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Gareth G. Hougham, Kamalesh K. Srivastava, Sung K. Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey, Donald W. Henderson, David R. Di Milia, Richard P. Ferlita, Roy A. Carruthers
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Publication number: 20100062597Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.Type: ApplicationFiled: October 5, 2009Publication date: March 11, 2010Inventors: Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith, Donald W. Henderson, Sung Kwon Kang, Eric H. Laine, Christian Lavoie, Paul A. Lauro, Valérie Anne Oberson, Da-Yuan Shih, Kamalesh K. Srivastava, Michael J. Sullivan
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Publication number: 20090266447Abstract: Semiconductor packaging techniques are provided which optimize metallurgical properties of a joint using dissimilar solders. A solder composition for Controlled Collapse Chip Connection processing includes a combination of a tin based lead free solder component designed for a chip and a second solder component designed for a laminate. The total concentration of module Ag after reflow is less than 1.9% by weight. A method of manufacturing a solder component is also provided.Type: ApplicationFiled: April 29, 2008Publication date: October 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JAMES A. BUSBY, MINHUA LU, VALERIE A. OBERSON, ERIC D. PERFECTO, KAMALESH K. SRIVASTAVA, BRIAN R. SUNDLOF, JULIEN SYLVESTRE, RENEE L. WEISMAN
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Patent number: 7572726Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: GrantFiled: November 10, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith, Randolph F. Knarr, Sarah H. Knickerbocker, Kevin S. Petrarca, Roger A. Quon, Wolfgang Sauter, Kamalesh K. Srivastava, Richard P. Volant
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Publication number: 20090163019Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.Type: ApplicationFiled: January 2, 2009Publication date: June 25, 2009Applicant: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Publication number: 20090146316Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.Type: ApplicationFiled: December 5, 2007Publication date: June 11, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Virendra R. Jadhav, Jayshree Shah, Kamalesh K. Srivastava
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Publication number: 20090095502Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.Type: ApplicationFiled: October 11, 2007Publication date: April 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: VIRENDRA R. JADHAV, KRYSTYNA W. SEMKOW, KAMALESH K. SRIVASTAVA, BRIAN R. SUNDLOF
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Patent number: 7473997Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: GrantFiled: September 12, 2005Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Publication number: 20080290142Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state.Type: ApplicationFiled: May 23, 2007Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gareth G. Hougham, Kamalesh K. Srivastava, Sung K. Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey, Donald W. Henderson, David R. Di Milia, Richard P. Ferlita, Roy A. Carruthers
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Patent number: 7425278Abstract: An etchant which includes an aqueous solution of between about 30% and about 38% concentrated hydrogen peroxide, said percentages being by volume, based on the total volume of the solution; between about 3.5 ml and about 20 ml per liter of phosphoric acid; and an amount of potassium hydroxide to adjust the pH of the solution to between about 7.8 and about 9.1. The etchant is useful in removing a layer of an alloy of titanium and tungsten or a layer of tungsten from a precision surface.Type: GrantFiled: November 28, 2006Date of Patent: September 16, 2008Assignee: International Business Machines CorporationInventors: Krystyna Waleria Semkow, Anurag Jain, Kamalesh K. Srivastava