Abstract: A memory system is provided for accessing an array of polycide fuses. The memory system includes an access control circuit configured to individually program and read each of the polycide fuses in the array. Row and column decoding circuitry is provided to selectively connect one of the polycide fuses to the access control circuit in response to an address signal. In one embodiment, the access control circuit includes a partial sense amplifier circuit, which is completed by connecting one of the polycide fuses to the partial sense amplifier circuit. The completed sense amplifier circuit compares the resistance of the connected polycide fuse with a reference resistance to determine the state of the polycide fuse. The completed sense amplifier circuit provides an output signal representative of the state of the connected polycide fuse. The access control circuit also includes a programming transistor connected between an input/output supply voltage (VIO) and the partial sense amplifier circuit.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process.

Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: Non-volatile storage elements are provided in an array on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit. The non-volatile storage elements are either EEPROM floating gate transistor cells, or other EEPROM cells using standard low voltage CMOS devices.

Abstract: An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: Non-volatile storage elements are provided in an array on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are one-time programmable devices which are programmed by rupturing their gate oxide.

Abstract: A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: Non-volatile storage elements are provided on an integrated circuit, where the non-volatile storage elements are low voltage CMOS devices and hence compatible in a manufacturing sense with other similar transistors on an integrated circuit, thereby not requiring special types of transistors for the non-volatile storage. The non-volatile storage elements are either one-time programmable devices which are programmed by rupturing their gate oxide, EEPROM floating gate transistor cells, or other EEPROM cells.

Abstract: A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

Abstract: An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

Abstract: An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

Abstract: The present invention provides a memory cell which includes a pair of flash EEPROM cells. One flash EEPROM cell is programmed and the other flash EEPROM cell is simultaneously erased by a single programming pulse. Because the configuration memory cell includes flash EEPROM cells, and therefore is non-volatile, a power down does not require reprogramming or refreshing of the configuration bit stored in the memory cell.

Abstract: A redundancy control circuit enables the redundancy of a row or a column in a memory array such that no degradation in access time occurs. The redundancy circuit is further configured such that negligible power is consumed by the circuit during both a standby mode and a redundancy enable mode.

Abstract: A circuit senses the state of an EPROM cell transistor and drives an output lead in response thereto. The circuit comprises first and second sense amplifiers, each having inverting and noninverting input leads. The circuit also comprises a reference voltage lead coupled to the inverting lead of the first sense amplifier and the noninverting lead of the second sense amplifier. An EPROM cell transistor is connected to the noninverting lead of the first sense amplifier and the inverting lead of the second sense amplifier. The first sense amplifier is coupled to a first portion of a buffer circuit which couples the output lead to a VCC supply lead, while the second sense amplifier drives a second portion of a buffer circuit which coupled the output lead to ground.

Abstract: A static decoding circuit which may be utilized with E.sup.2 PROM arrays. The circuit utilizes predecoded address signals to generate signals to the word lines in read, program, erase and bulk erase modes. The circuit includes a low voltage to high voltage converter, CMOS switches and post decoders which include a p-channel device so that individual row lines may be erased as well as all the row lines. In the read mode, the selected word line goes to VCC and other go to zero. In the programming mode, the selected word line goes to VPP and the selected word line goes to zero and the unselected word lines go to VPP. In the bulk erase mode, all the word lines go to zero.

Abstract: A novel write circuit arrangement for an EEPROM type memory system operable in response to the difference between the information stored in each addressed cell and the information to the be stored therein during a writing cycle and writing information into only those addressed cells for which a difference exists regardless of whether the difference indicates to charge or discharge the cell. The arrangement also can simultaneously charge one cell of a byte while discharging another cell of the same byte.