Patents by Inventor Kan Cheng
Kan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8601416Abstract: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.Type: GrantFiled: June 28, 2012Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Cheng Kuo, Wei-Yi Hu, Jui-Feng Kuan, Yi-Kan Cheng
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Publication number: 20130290916Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu LEE, Feng Wei KUO, Ching-Shun YANG, Yi-Kan CHENG, Jui-Feng KUAN
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Publication number: 20130275927Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.Type: ApplicationFiled: May 23, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
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Publication number: 20130254726Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.Type: ApplicationFiled: May 24, 2013Publication date: September 26, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chang HSU, Ying-Yu SHEN, Wen-Ju YANG, Hsiao-Shu CHAO, Yi-Kan CHENG
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Publication number: 20130246986Abstract: A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.Type: ApplicationFiled: June 28, 2012Publication date: September 19, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Cheng KUO, Wei-Yi HU, Jui-Feng KUAN, Yi-Kan CHENG
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Publication number: 20130239070Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.Type: ApplicationFiled: April 22, 2013Publication date: September 12, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-I HUANG, Hsiao-Shu CHAO, Yi-Kan CHENG
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Publication number: 20130227501Abstract: In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool.Type: ApplicationFiled: February 27, 2012Publication date: August 29, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Shun YANG, Ze-Ming WU, Hsiao-Shu CHAO, Yi-Kan CHENG
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Publication number: 20130205266Abstract: A method comprises: accessing a persistent, machine readable storage medium containing data representing an integrated circuit (IC) design to be fabricated using multi-patterning; identifying at least one network of conductive patterns configured to transmit signals that substantially impact timing of at least one circuit in the IC; pre-grouping the at least one network of conductive patterns in a first group; and electronically providing data to an electronic design automation (EDA) tool to cause inclusion in a first single photomask of all portions of the patterns within the first group that are to be formed in a single layer of the IC, wherein the single layer is to be multi-patterned using at least two photomasks.Type: ApplicationFiled: February 3, 2012Publication date: August 8, 2013Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.Inventors: Wen-Hao Chen, Yuan-Te Hou, Yi-Kan Cheng
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Publication number: 20130191796Abstract: Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Hao CHEN, Yuan-Te HOU, Yi-Kan CHENG
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Patent number: 8495532Abstract: A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.Type: GrantFiled: March 31, 2011Date of Patent: July 23, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
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Publication number: 20130174112Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.Type: ApplicationFiled: February 10, 2012Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ming HO, Ke-Ying SU, Hsiao-Shu CHAO, Yi-Kan CHENG
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Patent number: 8473873Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.Type: GrantFiled: September 2, 2011Date of Patent: June 25, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8468470Abstract: A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop.Type: GrantFiled: September 21, 2011Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chang Hsu, Wen-Ju Yang, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8453095Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.Type: GrantFiled: July 6, 2011Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen, Chung-Hsing Wang
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Patent number: 8448100Abstract: A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.Type: GrantFiled: April 11, 2012Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Lung Lin, Chin-Chang Hsu, Ying-Yu Shen, Wen-Ju Yang, Hsiao-Shu Chao, Yi-Kan Cheng, Chin-Hsiung Hsu, Huang-Yu Chen, Yi-Chuin Tsai, Yuan-Te Hou, Chung-Hsing Wang
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Patent number: 8448120Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.Type: GrantFiled: May 9, 2011Date of Patent: May 21, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-I Huang, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8434043Abstract: The present disclosure relates to a method and apparatus for identifying pre-coloring violations and for providing hints and/or warnings to a designer to eliminate the pre-coloring violations. In some embodiments, the method is performed by identifying G0-spaces within a double patterning technology (DPT) layer, of an integrated chip (IC) layout, having a plurality of pre-colored shapes. Violation paths extending between the pre-colored shapes are identified based upon the G0-spaces. Good paths (i.e., paths that will not cause a violation) and bad paths (i.e., paths that will cause a violation) between the pre-colored shapes are also identified. Hints and/or warnings are generated based upon the identified good and bad paths, wherein the hints and/or warnings provide guidance to eliminate the violation paths and develop a violation free IC layout.Type: GrantFiled: May 25, 2012Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chang Hsu, HungLung Lin, Wen-Ju Yang, Hsiao-Shu Chao, Yi-Kan Cheng
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Publication number: 20130091476Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.Type: ApplicationFiled: October 10, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huang-Yu CHEN, Yuan-Te HOU, Chung-Min FU, Chung-Hsing WANG, Wen-Hao CHEN, Yi-Kan CHENG
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Patent number: 8418098Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.Type: GrantFiled: March 24, 2008Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Heng Huang, Gary Lin, Chu-Fu Chen, Yi-Kan Cheng, Fu-Lung Hsueh
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Patent number: 8418117Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.Type: GrantFiled: July 7, 2010Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Ho Che Yu, Chung-Hsing Wang, Hsiao-Shu Chao, Yi-Kan Cheng, Lee-Chung Lu