Abstract: A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Abstract: A vertical turbine comprising a blade control mechanism including a sun gear engaging a plurality of planetary gears each coupled to blade assemblies. The sun gear has at least half circumference of its teeth removed, as the turbine receives maximum downstream torque in the circumference with teeth and it leaves blades free to rotate in the circumference without teeth for minimum upstream drag. The turbine converts the rotational blades into parallel movement and unidirectional propulsion with minimum turbulence.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.

Abstract: A method of a layout diagram (of a conductive line structure for an IC) including: for a first set of pillar patterns included in an initial layout diagram that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which are non-overlapping of each other, which have long axes that are substantially collinear with a reference line, and which have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: A vertical wind turbine with rotatable wind blades. Under wind pressure, each blade is capable to rotate and stop at a specified location for optimal angle of attack towards the wind to improve the efficiency of the turbine. Each blade is divided into two unequal area of airfoils with the aerodynamic center of the blade located in the larger area trail end. Under wind pressure, the turbine frame would stop the blades at locations where each blade has an optimal angle of attack towards the wind. As a result, blades in the upwind force zone encounter minimal drag force to improve the efficiency of the turbine.

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

Abstract: An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nth conductive lines in an nth layer. The first pads and the second pads respectively are grouped into a first, a second and an nth group. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the nth group is connected to one of the second pads in the nth group by one of the nth conductive lines.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.