Patents by Inventor Kan Hu

Kan Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250063758
    Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Hsu-Kai CHANG, Sung-Li WANG, Kuan-Kan HU, Shuen-Shin LIANG, Kao-Feng LIN, Hung Pin LU, Yi-Ying LIU, Chuan-Hui SHEN
  • Publication number: 20250031419
    Abstract: Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.
    Type: Application
    Filed: July 17, 2023
    Publication date: January 23, 2025
    Inventors: Kuan-Kan Hu, Po-Chin Chang, Olivia Pei-Hua Lee, Ku-Feng Yang, Sung-Li Wang, Szuya Liao
  • Patent number: 12204777
    Abstract: Systems and methods for space allocation for block device compression are provided. In particular, a computing device may receive an allocation request to write the compressed data, select a range list adequate for serving the allocation request from a plurality of range list, dequeue a range entry from the selected range list to allocate free space for the compressed data, and allocate the free space corresponding to the range entry to the compressed data to serve the allocation request.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: January 21, 2025
    Assignee: Lemon Inc.
    Inventors: Ping Zhou, Kan Frankie Fan, Chaohong Hu, Longxiao Li, Hui Zhang, Fei Liu
  • Patent number: 12204750
    Abstract: The present disclosure describes techniques of metadata management for transparent block level compression. A first area may be created in a backend solid state drive. The first area may comprise a plurality of entries. The plurality of entries may be indexed by addresses of a plurality of blocks of uncompressed data. Each of the plurality of entries comprises a first part configured to store metadata and a second part configured to store compressed data. Each of the plurality blocks of uncompressed data may be compressed individually to generate a plurality of compressed blocks. Metadata and at least a portion of compressed data associated with each of the plurality of compressed blocks may be stored in one of the plurality of entries based on an address of a corresponding block of uncompressed data. A second area may be created in the backend solid state drive for storing the rest of the compressed data.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: January 21, 2025
    Assignee: Lemon Inc.
    Inventors: Ping Zhou, Chaohong Hu, Kan Frankie Fan, Fei Liu, Longxiao Li, Hui Zhang
  • Publication number: 20250006742
    Abstract: A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuting CHENG, Tzu Pei CHEN, Kuan-Kan HU, Shao-An WANG, Jung-Hao CHANG, Sung-Li WANG
  • Publication number: 20250006561
    Abstract: Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Che Chi SHIH, Ku-Feng YANG, Szuya LIAO
  • Publication number: 20250006803
    Abstract: A method includes forming a first transistor over a substrate, in which the first transistor includes first source/drain epitaxy structures; forming a second transistor over the first transistor, in which the second transistor includes second source/drain epitaxy structures; forming an opening extending through one of the second source/drain epitaxy structures and exposing a top surface of one of the first source/drain epitaxy structures; performing a first deposition process to form a first metal in the opening, in which a first void is formed in the first metal during the first deposition process; performing a first etching back process to the first metal until the first void is absent; and performing a second deposition process to form a second metal in the opening and over the first metal.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY,, LTD.
    Inventors: Yuting CHENG, Kuan-Kan HU, Tzu Pei CHEN, Chia-Hung CHU, Po-Chin CHANG, Sung-Li WANG
  • Patent number: 12170331
    Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: December 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Wei Chang, Chia-Hung Chu, Hsu-Kai Chang, Sung-Li Wang, Kuan-Kan Hu, Shuen-Shin Liang, Kao-Feng Lin, Hung Pin Lu, Yi-Ying Liu, Chuan-Hui Shen
  • Publication number: 20240379748
    Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Kuan-Kan Hu, Han-De Chen, Ku-Feng Yang, Chen-Fong Tsai, Chi On Chui, Szuya Liao
  • Publication number: 20240363421
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu LIN, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
  • Patent number: 12132079
    Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan Hu, Han-De Chen, Ku-Feng Yang, Chen-Fong Tsai, Chi On Chui, Szuya Liao
  • Publication number: 20240321883
    Abstract: Semiconductor structures and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first bottom source/drain feature and a second bottom source/drain feature disposed over a substrate, a plurality of bottom channel members extending between and in contact with the first bottom source/drain feature and the second bottom source/drain feature, a first bonding layer over the plurality of bottom channel members, a second bonding layer disposed directly on the first bonding layer, a first top source/drain feature disposed directly over the first bottom source/drain feature, a second top source/drain feature disposed directly over the second bottom source/drain feature, and a plurality of top channel members disposed over the second bonding layer and extending between and in contact with the first top source/drain feature and the second top source/drain feature.
    Type: Application
    Filed: July 27, 2023
    Publication date: September 26, 2024
    Inventors: Han-De Chen, Chen-Fong Tsai, Kuan-Kan Hu, Ku-Feng Yang, Chi On Chui
  • Publication number: 20240282815
    Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
    Type: Application
    Filed: November 27, 2023
    Publication date: August 22, 2024
    Inventors: Kuan-Kan Hu, Han-De Chen, Ku-Feng Yang, Chen-Fong Tsai, Chi On Chui, Szuya Liao
  • Publication number: 20240282814
    Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
    Type: Application
    Filed: December 21, 2023
    Publication date: August 22, 2024
    Inventors: Kuan-Kan Hu, Han-De Chen, Ku-Feng Yang, Chen-Fong Tsai, Chi On Chui, Szuya Liao
  • Patent number: 12062576
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: August 13, 2024
    Inventors: Han-Yu Lin, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
  • Patent number: 12009011
    Abstract: The present disclosure describes techniques of presenting audio/video (AV) files. The disclosed techniques include displaying a first interface, wherein the first interface comprises a list of a plurality of AV files and an editing area; generating a plot graph based at least in part on an input by a first user via the first interface, wherein the plot graph has a directed structure, and the at least one first type of AV file and the at least one second type of AV file are associated with different nodes of the plot graph; playing a first type of AV file; detecting that a preset instruction is received in response to determining that a playing progress of the first type of AV file reaches a first predetermined position; and playing another first type of AV file or a second type of AV file based on the preset instruction.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 11, 2024
    Assignee: SHANGHAI BILIBILI TECHNOLOGY CO., LTD.
    Inventors: Huyang Sun, Zhaoxin Tan, Weijia Li, Jiangiang Ding, Yifei Pei, Yuxuan Gao, Kan Hu, Xiaofeng Ji, Chaoran Li, Fuling Chen, Dejun Shan
  • Patent number: 11952039
    Abstract: An electric-vehicle frame includes a mid-section and an end section. The mid-section has first and second frame rails spaced from each other by a first distance along a cross-vehicle axis defining a battery compartment therebetween. The end-section has first and second frame rails spaced from each other by a second distance along the cross-vehicle axis smaller than the first distance. A first connector is fixed to the first frame rail of the mid-section and to the first frame rail of the end-section. A second connector is fixed to the second frame rail of the mid-section and to the second frame rail of the end-section.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: April 9, 2024
    Assignee: Ford Global Technologies, LLC
    Inventors: Ajay Kumar Gupta, Leonard Anthony Shaner, Yu Liu, John Wesley Stanley, Yu-Kan Hu, Fungtai Charles Ko, Petros Frantzeskakis
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20240038595
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Jhih-Rong HUANG, Yi-Bo LIAO, Shuen-Shin LIANG, Min-Chiang CHUANG, Sung-Li WANG, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240014282
    Abstract: A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process. The selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer. The metal component is deposited on the catalyst layer. Exemplary selectivity enhancement processes include a self-assembled monolayer (SAM), introducing an accelerator, and/or introducing a suppressor.
    Type: Application
    Filed: January 26, 2023
    Publication date: January 11, 2024
    Inventors: Kuan-Kan HU, Tsung-Kai CHIU, Wei-Yen WOON, Szuya LIAO, Ku-Feng YANG