Patents by Inventor Kan Takeuchi

Kan Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11821795
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 21, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Yoshio Takazawa, Fumio Tsuchiya, Daisuke Oshida, Naoya Ota, Masaki Shimada, Shinya Konishi
  • Patent number: 11407920
    Abstract: An object of the present invention is to provide a paint which is excellent in various performances such as resistance to various organic solvents and hydraulic fluid, corrosion resistance, weather resistance, heat resistance, adhesion to substrates, and coating film appearance, and which in particular, can be suitably used for aircraft applications. Specifically, the invention provides a paint which contains, as an essential component of a main agent, a polyester resin (A) having a hydroxyl value in a range of 150 to 400 mg KOH/g and a weight average molecular weight (Mw) in a range of 500 to 5,000, and a polyisocyanate compound (B) as an essential component of a curing agent; an aircraft paint using the paint; and an aircraft using the aircraft paint.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 9, 2022
    Assignee: DIC Corporation
    Inventors: Kan Takeuchi, Ikue Hamamoto
  • Patent number: 11125628
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Shinya Konishi, Fumio Tsuchiya, Masaki Shimada
  • Patent number: 11068330
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Ota, Kan Takeuchi, Fumio Tsuchiya, Masaki Shimada, Shinya Konishi, Daisuke Oshida
  • Publication number: 20210080330
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 18, 2021
    Inventors: Kan TAKEUCHI, Yoshio TAKAZAWA, Fumio TSUCHIYA, Daisuke OSHIDA, Naoya OTA, Masaki SHIMADA, Shinya KONISHI
  • Publication number: 20210017417
    Abstract: An object of the present invention is to provide a paint which is excellent in various performances such as resistance to various organic solvents and hydraulic fluid, corrosion resistance, weather resistance, heat resistance, adhesion to substrates, and coating film appearance, and which in particular, can be suitably used for aircraft applications. Specifically, the invention provides a paint which contains, as an essential component of a main agent, a polyester resin (A) having a hydroxyl value in a range of 150 to 400 mg KOH/g and a weight average molecular weight (Mw) in a range of 500 to 5,000, and a polyisocyanate compound (B) as an essential component of a curing agent; an aircraft paint using the paint; and an aircraft using the aircraft paint.
    Type: Application
    Filed: December 6, 2018
    Publication date: January 21, 2021
    Inventors: Kan Takeuchi, Ikue Hamamoto
  • Publication number: 20200081757
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 12, 2020
    Inventors: Naoya OTA, Kan TAKEUCHI, Fumio TSUCHIYA, Masaki SHIMADA, Shinya KONISHI, Daisuke OSHIDA
  • Patent number: 10396802
    Abstract: In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Mitsuhiko Igarashi, Kan Takeuchi, Takeshi Okagaki
  • Patent number: 10361685
    Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Yoshio Takazawa
  • Patent number: 10310007
    Abstract: An object of the invention is to provide a semiconductor apparatus capable of achieving conditions that are stricter than the conditions in which the stable operation is guaranteed, without increasing the circuit size. A semiconductor apparatus (10) includes a semiconductor circuit (11); a voltage generator (12) that selects one of at least two types of voltages and applies a power supply voltage, the at least two types of voltages including a normal voltage at which the semiconductor circuit (11) normally operates and a low voltage which is lower than the normal voltage; and a clock generator (13) that supplies the semiconductor circuit (11) with a clock signal having a constant frequency regardless of the power supply voltage.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 4, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaki Shimada, Kan Takeuchi
  • Publication number: 20190154518
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Application
    Filed: September 10, 2018
    Publication date: May 23, 2019
    Inventors: Kan TAKEUCHI, Shinya KONISHI, Fumio TSUCHIYA, Masaki SHIMADA
  • Patent number: 10211620
    Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kan Takeuchi, Mitsuhiko Igarashi, Makoto Ogasawara
  • Publication number: 20180156859
    Abstract: To provide a semiconductor device that can predict wear-out failure with high accuracy based on an accumulated value of degradation stress, such as a power-source voltage or an environmental temperature, imposed to the semiconductor device, the semiconductor device includes a first circuit that holds a first accumulated degradation stress count value, a second circuit that holds a second accumulated degradation stress count value, a third circuit that holds a count value of an accumulated operating time or a value corresponding thereto, and a fourth circuit or an operating unit that receives the first accumulated degradation stress count value, the second accumulated degradation stress count value, and the count value of the accumulated operating time or the value corresponding to the value of the accumulated operating time.
    Type: Application
    Filed: October 27, 2017
    Publication date: June 7, 2018
    Inventors: Kan Takeuchi, Fumio Tsuchiya, Shinya Konishi
  • Publication number: 20170327720
    Abstract: The invention provides an adhesive coating material which realizes excellent adhesive strength and moist-heat resistance at the time of bonding a solar cell sealing material and a base sheet, a polyol composition for the coating material, a cured object of the adhesive coating material, an adhesive sheet obtained by being coated with adhesive coating material, and a solar cell module using the sheet. As a polyol component of the adhesive coating material which forms an adhesive layer b in a back sheet E of the solar cell module illustrated in Figure, a hydroxyl group-containing (meth)acrylic resin (I) and unsaturated double bond-containing polyester polyol (II) are used as essential components.
    Type: Application
    Filed: February 25, 2016
    Publication date: November 16, 2017
    Applicant: DIC CORPORATION
    Inventors: Miho Takeda, Takatoshi Matsuo, Tatsuya Kouyama, Kan Takeuchi, Yasunobu Hirota
  • Publication number: 20170187358
    Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 29, 2017
    Inventors: Kan TAKEUCHI, Masaki SHIMADA, Takeshi OKAGAKI, Yoshio TAKAZAWA
  • Publication number: 20170063075
    Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.
    Type: Application
    Filed: July 22, 2016
    Publication date: March 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Kan TAKEUCHI, Mitsuhiko IGARASHI, Makoto OGASAWARA
  • Publication number: 20170038426
    Abstract: In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.
    Type: Application
    Filed: June 10, 2016
    Publication date: February 9, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Mitsuhiko IGARASHI, Kan TAKEUCHI, Takeshi OKAGAKI
  • Publication number: 20160291078
    Abstract: An object of the invention is to provide a semiconductor apparatus capable of achieving conditions that are stricter than the conditions in which the stable operation is guaranteed, without increasing the circuit size. A semiconductor apparatus (10) includes a semiconductor circuit (11); a voltage generator (12) that selects one of at least two types of voltages and applies a power supply voltage, the at least two types of voltages including a normal voltage at which the semiconductor circuit (11) normally operates and a low voltage which is lower than the normal voltage; and a clock generator (13) that supplies the semiconductor circuit (11) with a clock signal having a constant frequency regardless of the power supply voltage.
    Type: Application
    Filed: December 17, 2015
    Publication date: October 6, 2016
    Inventors: Masaki SHIMADA, Kan TAKEUCHI
  • Patent number: 8791214
    Abstract: A low dielectric constant, a low dielectric loss tangent, and heat resistance are achieved. An active ester resin that has a resin structure produced by reacting a polyfunctional phenolic compound (a1) with a monofunctional aromatic carboxylic acid or its chloride (a2) and an aromatic dicarboxylic acid or its chloride (a3). The polyfunctional phenolic compound (a1) is represented by structural formula (1) below: (where Ar represents a benzene ring, a naphthalene ring, a benzene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, or a naphthalene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, X represents a methylene group, a divalent cyclic aliphatic hydrocarbon group, a phenylene dimethylene group, or a biphenylene-dimethylene group, and n represents the number of repeating units and the average thereof is in a range of 0.5 to 10).
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: July 29, 2014
    Assignee: DIC Corporation
    Inventors: Kan Takeuchi, Etsuko Suzuki, Kunihiro Morinaga, Kazuo Arita
  • Publication number: 20140151094
    Abstract: A low dielectric constant, a low dielectric loss tangent, and heat resistance are achieved. An active ester resin that has a resin structure produced by reacting a polyfunctional phenolic compound (a1) with a monofunctional aromatic carboxylic acid or its chloride (a2) and an aromatic dicarboxylic acid or its chloride (a3). The polyfunctional phenolic compound (a1) is represented by structural formula (1) below: (where Ar represents a benzene ring, a naphthalene ring, a benzene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, or a naphthalene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, X represents a methylene group, a divalent cyclic aliphatic hydrocarbon group, a phenylene dimethylene group, or a biphenylene-dimethylene group, and n represents the number of repeating units and the average thereof is in a range of 0.5 to 10).
    Type: Application
    Filed: May 25, 2012
    Publication date: June 5, 2014
    Applicant: DIC Corporation
    Inventors: Kan Takeuchi, Etsuko Suzuki, Kunihiro Morinaga, Kazuo Arita