Patents by Inventor Kandabara Tapily

Kandabara Tapily has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200118871
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 16, 2020
    Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
  • Publication number: 20200098897
    Abstract: A semiconductor device herein includes doped extension regions for silicon and silicon germanium nanowires. The nanowires can be selectively grown and recessed into a gate spacer. The semiconductor device can include a gate structure including the gate spacer; the nanowire or channel extending through the gate structure such that an end of the channel is recessed within a recess in said gate spacer; an extension region in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel; and a source-drain contact in contact with the extension region and adjacent to the gate structure.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Kandabara Tapily, Jeffrey Smith, Nihar Mohanty, Anton J. deVilliers
  • Publication number: 20200083080
    Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The systems process chambers are connected to each other via transfer chambers used to move the workpieces, in the controlled environment, between the process chambers. The transfer chambers include a measurement module capable of measuring workpiece attributes before and/or after process treatments. The measurement module may include an inspection system mounted above, below, or inside the transfer chamber.
    Type: Application
    Filed: March 18, 2019
    Publication date: March 12, 2020
    Inventors: Robert Clark, Kandabara Tapily
  • Publication number: 20200081423
    Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.
    Type: Application
    Filed: March 18, 2019
    Publication date: March 12, 2020
    Inventors: Robert Clark, Jeffrey Smith, Kandabara Tapily, Angelique Raley, Qiang Zhao
  • Publication number: 20200083070
    Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). This system includes a distributed transfer system for transferring workpieces between The processing modules may include, one or more film-forming modules, etch modules, batch processing module, cleaning module, or any combination thereof. Further, the distributed transfer system include inspection system to measure attributes on the workpiece before and/or after being treated in the processing modules.
    Type: Application
    Filed: March 18, 2019
    Publication date: March 12, 2020
    Inventors: Robert Clark, Kandabara Tapily
  • Publication number: 20200083074
    Abstract: This disclosure relates to a method for using a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing method can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.
    Type: Application
    Filed: March 18, 2019
    Publication date: March 12, 2020
    Inventors: Robert Clark, Jeffrey Smith, Kandabara Tapily, Angelique Raley, Qiang Zhao
  • Patent number: 10586734
    Abstract: A substrate processing method for forming fully self-aligned vias. The method may be performed in a batch processing system that is capable of simultaneously processing multiple substrates, where the batch processing system includes a process chamber containing processing spaces defined around an axis of rotation in the process chamber. Each of the substrates contain a first surface and a second surface, and the method includes selectively forming SiO2 raised features on the first surface relative to the second surface.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 10, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara Tapily
  • Patent number: 10586765
    Abstract: Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric cap that isolates the power rail from conductive pattern structures on the dielectric cap. Further, an opening is selectively formed in the dielectric cap and is filled with conductive material to selectively connect a conductive pattern structure with the power rail.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 10, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. Devilliers, Kandabara Tapily
  • Publication number: 20200075574
    Abstract: A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 5, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Anton J. DEVILLIERS, Kandabara TAPILY
  • Publication number: 20200075592
    Abstract: A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 5, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Publication number: 20200075489
    Abstract: A semiconductor device is provided. The semiconductor device includes a transistor stack having a plurality of transistor pairs that are stacked over a substrate. Each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. The semiconductor device further includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack and are electrically coupled to the transistor stack.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 5, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Anton J. deVilliers, Kandabara Tapily
  • Publication number: 20200035481
    Abstract: A substrate processing method is described for forming a titanium nitride material that may be used for superconducting metallization or work function adjustment applications. The substrate processing method includes depositing by vapor phase deposition at least one monolayer of a first titanium nitride film on a substrate, and treating the first titanium nitride film with plasma excited hydrogen-containing gas, where the first titanium nitride film is polycrystalline and the treating increases the (200) crystallographic texture of the first titanium nitride film. The method further includes depositing by vapor phase deposition at least one monolayer of a second titanium nitride film on the treated at least one monolayer of the first titanium nitride film, and treating the at least one monolayer of the second titanium nitride film with plasma excited hydrogen-containing gas.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 30, 2020
    Inventor: Kandabara Tapily
  • Patent number: 10529830
    Abstract: A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: January 7, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kandabara Tapily, Jeffrey Smith, Nihar Mohanty, Anton J. Devilliers
  • Publication number: 20200006140
    Abstract: In a method for processing a substrate, a conductive cap layer is selectively formed over a plurality of conductive structures that are positioned in a first dielectric layer. A second dielectric layer is selectively formed over the first dielectric layer. A third dielectric layer is selectively formed over the second dielectric layer. A fourth dielectric layer is then formed over the plurality of conductive structures and the third dielectric layer, and an interconnect structure is subsequently formed within the fourth dielectric layer. The interconnect structure includes a via structure that has a first portion positioned over the conductive cap layer so that sidewalls of the first portion are surrounded by the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Kandabara TAPILY, Jeffrey SMITH
  • Publication number: 20190393097
    Abstract: A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 26, 2019
    Inventors: Kandabara Tapily, Jeffrey Smith, Gerrit Leusink
  • Publication number: 20190385906
    Abstract: A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Inventors: Hirokazu Aizawa, Karthikeyan Pillai, Nicholas Joy, Kandabara Tapily
  • Publication number: 20190333763
    Abstract: A method of area selective deposition for cap layer formation in advanced semiconductor contacts. The method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized metal layer. The selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 31, 2019
    Inventors: Kandabara Tapily, Gerrit Leusink, Takaaki Tsunomura
  • Patent number: 10460988
    Abstract: A removal method is provided for selectively removing a plurality of types of metal oxide films in a plurality of recesses formed in a substrate that is arranged in a processing chamber. The removal method includes repeatedly performing process steps of exposing the plurality of types of metal oxide films to BCl3 gas or a BCl3 gas plasma generated by introducing BCl3 gas, stopping introduction of the BCl3 gas and performing a purge process, exposing the plurality of types of metal oxide films and/or a plurality of types of metal films underneath the metal oxide films to one or more different plasmas, at least one of which is generated by introducing a single gas of an inert gas, and stopping introduction of the inert gas and performing the purge process.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 29, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Itatani, Tadahiro Ishizaka, Kandabara Tapily, Kai-Hung Yu, Wanjae Park
  • Publication number: 20190311947
    Abstract: A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Inventors: Kandabara Tapily, Takaaki Tsunomura
  • Publication number: 20190295870
    Abstract: A substrate processing tool configured for performing integrated substrate processing and substrate metrology, and methods of processing a substrate. The substrate processing tool includes a substrate transfer chamber, a plurality of substrate processing chambers coupled to the substrate transfer chamber, and a substrate metrology module coupled to the substrate transfer chamber. A substrate processing method includes processing a substrate in a first substrate processing chamber of a substrate processing tool, transferring the substrate from the first substrate processing chamber through a substrate transfer chamber to a substrate metrology module in the substrate processing tool, performing metrology on the substrate in the substrate metrology module, transferring the substrate from the substrate metrology module to a second substrate processing chamber through the substrate transfer chamber, and processing the substrate in the second substrate processing chamber.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 26, 2019
    Inventors: Kandabara Tapily, Robert Clark