Patents by Inventor Kanetake Takasaki
Kanetake Takasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6984267Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.Type: GrantFiled: September 6, 2002Date of Patent: January 10, 2006Assignee: Fujitsu LimitedInventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
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Patent number: 6780699Abstract: A semiconductor device in which the insulation characteristics of an insulating film of multilayer structure including a lower-layer insulating film and a high-dielectric-constant film formed on the lower-layer insulating film are ensured, and a method for fabricating such a semiconductor device. A silicon oxide film or a silicon oxynitride film is formed on a semiconductor substrate as a lower-layer insulating film and part of the lower-layer insulating film is removed. Then a high-dielectric-constant film the dielectric constant of which is higher than that of the lower-layer insulating film is formed on the exposed semiconductor substrate and the lower-layer insulating film. If the lower-layer insulating film is a silicon oxide film, then a metallic compound not including chlorine is used for forming this high-dielectric-constant film. If the lower-layer insulating film is a silicon oxynitride film, then a metallic chloride can be used for forming this high-dielectric-constant film.Type: GrantFiled: February 6, 2003Date of Patent: August 24, 2004Assignee: Fujitsu LimitedInventors: Yasuyuki Tamura, Yusuke Morisaki, Yoshihiro Sugita, Kiyoshi Irino, Takayuki Aoyama, Chikako Yoshida, Yoshihiro Sugiyama, Hitoshi Tanaka, Kanetake Takasaki
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Publication number: 20030168697Abstract: A semiconductor device in which the insulation characteristics of an insulating film of multilayer structure including a lower-layer insulating film and a high-dielectric-constant film formed on the lower-layer insulating film are ensured, and a method for fabricating such a semiconductor device. A silicon oxide film or a silicon oxynitride film is formed on a semiconductor substrate as a lower-layer insulating film and part of the lower-layer insulating film is removed. Then a high-dielectric-constant film the dielectric constant of which is higher than that of the lower-layer insulating film is formed on the exposed semiconductor substrate and the lower-layer insulating film. If the lower-layer insulating film is a silicon oxide film, then a metallic compound not including chlorine is used for forming this high-dielectric-constant film. If the lower-layer insulating film is a silicon oxynitride film, then a metallic chloride can be used for forming this high-dielectric-constant film.Type: ApplicationFiled: February 6, 2003Publication date: September 11, 2003Applicant: FUJITSU LIMITEDInventors: Yasuyuki Tamura, Yusuke Morisaki, Yoshihiro Sugita, Kiyoshi Irino, Takayuki Aoyama, Chikako Yoshida, Yoshihiro Sugiyama, Hitoshi Tanaka, Kanetake Takasaki
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Publication number: 20030022523Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.Type: ApplicationFiled: September 6, 2002Publication date: January 30, 2003Applicant: FUJITSU LIMITEDInventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
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Patent number: 6468926Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.Type: GrantFiled: June 29, 1999Date of Patent: October 22, 2002Assignee: Fujitsu LimitedInventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
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Patent number: 5424243Abstract: A method of producing a compound semiconductor crystal-on-substrate structure includes forming a first compound semiconductor crystal layer made of a group III-V compound semiconductor on a Si substrate, forming a stacked structure by forming an amorphous compound semiconductor layer made of the group III-V compound semiconductor on the first compound semiconductor crystal layer, subjecting the stacked structure to a thermal process, removing at least the amorphous compound semiconductor layer from the stacked structure that is subjected to the thermal process, and forming a second compound semiconductor crystal layer made of the group III-V compound semiconductor, to thereby form the compound semiconductor crystal-on-substrate structure.Type: GrantFiled: September 9, 1994Date of Patent: June 13, 1995Assignee: Fujitsu LimitedInventor: Kanetake Takasaki
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Patent number: 5312783Abstract: A process for the preparation of a high dielectric thin film. A tantalum oxide film is formed on a substrate at a temperature of from 400.degree. to 850.degree. C. by means of an electron cyclotron resonance plasma chemical vapor deposition (ECR plasma CVD) method. A high dielectric film having little leakage current, good surface flatness and good step coverage is obtained.Type: GrantFiled: May 28, 1992Date of Patent: May 17, 1994Assignee: Fujitsu LimitedInventors: Kanetake Takasaki, Satoshi Nakai
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Patent number: 5210052Abstract: A method for fabricating a heteroepitaxial semiconductor substrate body used as a substrate of a compound semiconductor device. The heteroepitaxial semiconductor substrate body comprises a semiconductor substrate of a first semiconductor material and an epitaxial layer of a second semiconductor material grown heteroepitaxially on the semiconductor substrate. The method comprises steps of growing the epitaxial layer on the semiconductor substrate heteroepitaxially to form the heteroepitaxial semiconductor substrate body, depositing a stress inducing layer on a top surface of the epitaxial layer so as to induce a stress in the epitaxial layer, applying a cyclic annealing process for repeatedly and alternately holding the heteroepitaxial substrate body including the stress inducing layer deposited on the epitaxial layer at a first temperature and at a second temperature lower than the first temperature, and removing the stress inducing layer from the top surface of the epitaxial layer.Type: GrantFiled: May 13, 1992Date of Patent: May 11, 1993Assignee: Fujitsu LimitedInventor: Kanetake Takasaki
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Patent number: 5183778Abstract: A semiconductor device is produced by forming a crystalline substrate of a first layer of Si and a second layer of GaAs or GaAs-containing compound formed on the first layer, wherein a Ge or Ge-containing crystalline layer is formed as an intervening layer between the second layer and the first layer.Type: GrantFiled: December 30, 1991Date of Patent: February 2, 1993Assignee: Fujitsu LimitedInventor: Kanetake Takasaki
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Patent number: 5107317Abstract: A semiconductor device comprises a crystalline substrate with a silicon surface, a first buffer layer of GaAs or GaAs-containing compound formed on the Si surfaces and a second buffer layer of a Ge or Ge-containing crystalline layer formed as an intervening layer between the first layer and a compound semiconductor layer.Type: GrantFiled: November 20, 1990Date of Patent: April 21, 1992Assignee: Fujitsu Ltd.Inventor: Kanetake Takasaki
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Patent number: 5057880Abstract: A semiconductor device comprises a substrate, a compound semiconductor layer provided on the substrate, and an active region formed on the compound semiconductor layer. The substrate in turn comprises a first semiconductor layer of a first semiconductor material, a second semiconductor layer of a second semiconductor material and provided on the first semiconductor layer, and a third semiconductor layer provided on the second semiconductor layer. The third semiconductor layer has a plurality of segments each defined by a pair of side walls that extend substantially perpendicular to the third semiconductor layer. The plurality of segments have a plurality of first-type segments and a plurality of second-type segments wherein the first- and second-type segments are arranged alternately when viewed in a direction parallel to the third semiconductor layer.Type: GrantFiled: October 23, 1990Date of Patent: October 15, 1991Assignee: Fujitsu LimitedInventors: Takashi Eshita, Toshikazu Inoue, Kanetake Takasaki
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Patent number: 5019529Abstract: A heteroepitaxial growth method wherein a III-V group compound semiconductor is formed on a silicon substrate. A first amorphous III-V group compound semiconductor layer is formed on the silicon substrate before forming a III-V group compound semiconductor crystal layer on the amorphous III-V group compound semiconductor layer. A second amorphous III-V group semiconductor layer having a thickness greater than the crystal layer is formed on the III-V group compound semiconductor crystal layer and subjected to a solid phase epitaxial growth whereby the second amorphous III-V group compound semiconductor layer is made a single crystalline layer.Type: GrantFiled: May 2, 1989Date of Patent: May 28, 1991Assignee: Fujitsu LimitedInventor: Kanetake Takasaki
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Patent number: 4929985Abstract: A compound semiconductor device comprises: a III-V group compound semiconductor substrate and a Schottky junction electrode of p-type amorphous silicon carbide (a-SiC) layer provided on the III-V group compound semiconductor substrate and an amorphous silicon-germanium-boron (a-Si-Ge-B) layer provided on the p-type amorphous silicon carbide layer.Type: GrantFiled: May 2, 1989Date of Patent: May 29, 1990Assignee: Fujitsu LimitedInventor: Kanetake Takasaki
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Patent number: 4781945Abstract: A coating of phosphosilicate glass is deposited on a substrate by a chemical vapor deposition method, using a reaction gas consisting of monosilane, phosphine, and oxygen, in admixture with ammonia gas. According to this deposition process, the undesirable formation and adhesion of particulate by-products such as SiO.sub.2, P.sub.2 O.sub.5, and H.sub.2 SiO.sub.3 to the substrate surface can be effectively prevented, and the step coverage can be improved.Type: GrantFiled: June 23, 1987Date of Patent: November 1, 1988Assignee: Fujitsu LimitedInventors: Masahide Nishimura, Kanetake Takasaki, Kenji Koyama, Atsuhiro Tsukune
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Patent number: 4741919Abstract: A process for the preparation of a semiconductor device by the plasma chemical vapor deposition of amorphous silicon on a substrate, which comprises generating plasma in a deposition furnace by using a high frequency wave of less than 1 MHz to deposit an amorphous silicon film, and generating oxygen plasma in the same deposition furnace and irradiating the amorphous silicon film with the oxygen plasma.Type: GrantFiled: July 24, 1987Date of Patent: May 3, 1988Assignee: Fujitsu LimitedInventor: Kanetake Takasaki
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Patent number: 4581622Abstract: A silicon nitride film containing from 20 to 70% oxygen, for use as a surface passivation film, has enhanced ultraviolet ray transmissivity while exhibiting the desirable moisture proofness quality of a silicon nitride film.Type: GrantFiled: February 13, 1984Date of Patent: April 8, 1986Assignee: Fujitsu LimitedInventors: Kanetake Takasaki, Mikio Takagi, Kenji Koyama
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Patent number: 4539068Abstract: A plasma chemical vapor deposition method for forming a film on a substrate which is placed on one of a pair of electrodes oppositely arranged within the reaction chamber of a reactor. A plurality of power generators of different frequencies are applied to the electrodes to excite reactive gases introduced into the reaction chamber, whereby the reactive gases are transformed into a plasma and a desired film is formed on the substrate. Film with a small number of pinholes was formed at a relatively high deposition rate by combinations of power generator frequencies of, for example, 13.56 MHz and 1 MHz, 13.56 MHz and 50 KHz, and 5 MHz and 400 KHz.Type: GrantFiled: August 27, 1982Date of Patent: September 3, 1985Assignee: Fujitsu LimitedInventors: Mikio Takagi, Kanetake Takasaki, Kenji Koyama
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Patent number: 4532022Abstract: A silicon nitride film containing from 20 to 70% oxygen, for use as a surface passivation film, has enhanced ultraviolet ray transmissivity while exhibiting the desirable moisture proofness quality of a silicon nitride film.Type: GrantFiled: May 31, 1983Date of Patent: July 30, 1985Assignee: Fujitsu LimitedInventors: Kanetake Takasaki, Mikio Takagi, Kenji Koyama
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Patent number: 4406053Abstract: A process for manufacturing a semiconductor device comprises the step of annealing a porous passivation layer which is deposited on the surface of the device and which covers metallization layers fabricated thereon, by irradiating a laser beam on the passivation layer so as to densify the passivation layer, while the laser beam scans the surface of the passivation layer.Type: GrantFiled: July 31, 1981Date of Patent: September 27, 1983Assignee: Fujitsu LimitedInventors: Kanetake Takasaki, Yoshimi Shioya
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Patent number: 4394401Abstract: A method of plasma enhanced chemical vapor deposition of a phosphosilicate glass film on a substrate from a reaction gas mixture including SiH.sub.4, N.sub.2 O and PH.sub.3 is disclosed. This deposition is effected under the conditions such that a mol ratio of N.sub.2 O to SiH.sub.4 (N.sub.2 O/SiH.sub.4) in the reaction gas mixture is 50 or more and that a mol ratio of PH.sub.3 to SiH.sub.4 (PH.sub.3 /SiH.sub.4) in the reaction gas mixture is 0.08 or less. In the phosphosilicate glass film thus deposited, no cracking occurs due to a high temperature heat-treatment and due to the stress, caused by cooling the deposited films to an ordinarily ambient temperature.Type: GrantFiled: August 7, 1981Date of Patent: July 19, 1983Assignee: Fujitsu LimitedInventors: Yoshimi Shioya, Mamoru Maeda, Kanetake Takasaki, Mikio Takagi