Patents by Inventor Kaneyoshi Takeshita

Kaneyoshi Takeshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9806121
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 31, 2017
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Publication number: 20160351613
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Application
    Filed: August 8, 2016
    Publication date: December 1, 2016
    Inventors: KAZUKI NOMOTO, KANEYOSHI TAKESHITA, HIROYUKI OHRI
  • Patent number: 9455295
    Abstract: There is provided a solid-state image sensor including a plurality of unit pixels arranged thereon, the plurality of unit pixels each including a light receiving section which stores a charge generated by photoelectric conversion, a signal storage section which is connected to the light receiving section and has a structure of a MOS capacitor, and a signal output section to which a gate electrode of the MOS capacitor is connected.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: September 27, 2016
    Assignee: SONY CORPORATION
    Inventors: Kaneyoshi Takeshita, Kazuki Nomoto
  • Patent number: 9437641
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: September 6, 2016
    Assignee: SONY CORPORATION
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Publication number: 20150325617
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Application
    Filed: April 16, 2015
    Publication date: November 12, 2015
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Patent number: 9029926
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: May 12, 2015
    Assignee: Sony Corporation
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Publication number: 20140253765
    Abstract: A signal processing unit includes: an extraction section configured to extract variation between a plurality of sampling values obtained through a plurality of sampling operations of signal levels in one or both of a first state and a second state, the first state being a state where floating diffusion is reset, the floating diffusion temporarily accumulating charges transferred from a photodiode performing photoelectric conversion, and the second state being a state where charges generated in the photodiode are accumulated in the floating diffusion; and a comparison section configured to compare the variation extracted by the extraction section and a predetermined reference value, and to switch, based on a result of the comparison, a signal to be output to a processing section in a subsequent stage.
    Type: Application
    Filed: February 18, 2014
    Publication date: September 11, 2014
    Applicant: SONY CORPORATION
    Inventors: Kaneyoshi Takeshita, Kazuki Nomoto, Kenichi Nishio
  • Publication number: 20140117429
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Application
    Filed: December 31, 2013
    Publication date: May 1, 2014
    Applicant: SONY CORPORATION
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Patent number: 8633524
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: January 21, 2014
    Assignee: Sony Corporation
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Patent number: 8629385
    Abstract: Disclosed herein is a solid-state imaging element including: (A) a light reception/charge storage region formed in a semiconductor layer, the light reception/charge storage region including M light reception/charge storage layers stacked one on top of the other, where M?2; (B) a charge output region formed in the semiconductor layer; (C) a conduction/non-conduction control region which includes a portion of the semiconductor layer located between the light reception/charge storage region and the charge output region; and (D) a conduction/non-conduction control electrode adapted to control the conduction or non-conduction state of the conduction/non-conduction control region, wherein mth potential control electrodes are provided between the mth and (m+1)th light reception/charge storage layers, where 1?m?(M?1), to control the potentials of the light reception/charge storage layers.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: January 14, 2014
    Assignee: Sony Corporation
    Inventors: Kaneyoshi Takeshita, Takashi Kubodera, Akihiro Nakamura
  • Publication number: 20130277535
    Abstract: There is provided a solid-state image sensor including a plurality of unit pixels arranged thereon, the plurality of unit pixels each including a light receiving section which stores a charge generated by photoelectric conversion, a signal storage section which is connected to the light receiving section and has a structure of a MOS capacitor, and a signal output section to which a gate electrode of the MOS capacitor is connected.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 24, 2013
    Applicant: Sony Corporation
    Inventors: KANEYOSHI TAKESHITA, KAZUKI NOMOTO
  • Patent number: 8466990
    Abstract: An imaging apparatus includes: an imaging unit configured to image an image using an imaging device; an image obtaining unit configured to obtain a plurality of images equivalent to the time of dark, imaged by the imaging unit; a registering unit configured to register, with an image obtained by the image obtaining unit, the address and change amount of a pixel where the output value of the pixel changes so as to exceed a predetermined threshold; and a correcting unit configured to correct, when taking a pixel corresponding to an address registered by the registering unit as a processing object pixel, the pixel value of the processing object pixel based on comparison between difference of the output values of the processing object pixel and a peripheral pixel of the processing object pixel, and the change amount of the processing object pixel.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: June 18, 2013
    Assignee: Sony Corporation
    Inventors: Kazuki Nomoto, Akihiro Nakamura, Takashi Kubodera, Kaneyoshi Takeshita, Yukihiro Kiyota
  • Patent number: 8362412
    Abstract: A solid-state image pickup element includes: (A) a light receiving/charge accumulating region formed in a semiconductor layer and formed by laminating M (where M?2) light receiving/charge accumulating layers; (B) a charge outputting region formed in the semiconductor layer; (C) a depletion layer forming region formed of a part of the semiconductor layer, the part of the semiconductor layer being situated between the light receiving/charge accumulating region and the charge outputting region; and (D) a control electrode region for controlling a state of formation of a depletion layer in the depletion layer forming region, wherein the solid-state image pickup element further includes a light receiving/charge accumulating layer extending section extending from each light receiving/charge accumulating layer to the depletion layer forming region.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 29, 2013
    Assignee: Sony Corporation
    Inventors: Takashi Kubodera, Akihiro Nakamura, Kaneyoshi Takeshita
  • Publication number: 20120223405
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Application
    Filed: February 14, 2012
    Publication date: September 6, 2012
    Applicant: Sony Corporation
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Publication number: 20110102648
    Abstract: An imaging apparatus includes: an imaging unit configured to image an image using an imaging device; an image obtaining unit configured to obtain a plurality of images equivalent to the time of dark, imaged by the imaging unit; a registering unit configured to register, with an image obtained by the image obtaining unit, the address and change amount of a pixel where the output value of the pixel changes so as to exceed a predetermined threshold; and a correcting unit configured to correct, when taking a pixel corresponding to an address registered by the registering unit as a processing object pixel, the pixel value of the processing object pixel based on comparison between difference of the output values of the processing object pixel and a peripheral pixel of the processing object pixel, and the change amount of the processing object pixel.
    Type: Application
    Filed: August 4, 2010
    Publication date: May 5, 2011
    Applicant: Sony Corporation
    Inventors: Kazuki Nomoto, Akihiro Nakamura, Takashi Kubodera, Kaneyoshi Takeshita, Yukihiro Kiyota
  • Publication number: 20100213354
    Abstract: Disclosed herein is a solid-state imaging element including: (A) a light reception/charge storage region formed in a semiconductor layer, the light reception/charge storage region including M light reception/charge storage layers stacked one on top of the other, where M?2; (B) a charge output region formed in the semiconductor layer; (C) a conduction/non-conduction control region which includes a portion of the semiconductor layer located between the light reception/charge storage region and the charge output region; and (D) a conduction/non-conduction control electrode adapted to control the conduction or non-conduction state of the conduction/non-conduction control region, wherein mth potential control electrodes are provided between the mth and (m+1)th light reception/charge storage layers, where 1?m?(M?1), to control the potentials of the light reception/charge storage layers.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 26, 2010
    Applicant: SONY CORPORATION
    Inventors: Kaneyoshi Takeshita, Takashi Kubodera, Akihiro Nakamura
  • Publication number: 20100176277
    Abstract: A solid-state image pickup element includes: (A) a light receiving/charge accumulating region formed in a semiconductor layer and formed by laminating M (where M?2) light receiving/charge accumulating layers; (B) a charge outputting region formed in the semiconductor layer; (C) a depletion layer forming region formed of a part of the semiconductor layer, the part of the semiconductor layer being situated between the light receiving/charge accumulating region and the charge outputting region; and (D) a control electrode region for controlling a state of formation of a depletion layer in the depletion layer forming region, wherein the solid-state image pickup element further includes a light receiving/charge accumulating layer extending section extending from each light receiving/charge accumulating layer to the depletion layer forming region.
    Type: Application
    Filed: December 23, 2009
    Publication date: July 15, 2010
    Applicant: Sony Corporation
    Inventors: Takashi Kubodera, Akihiro Nakamura, Kaneyoshi Takeshita
  • Patent number: 6376917
    Abstract: A semiconductor device is characterized by mixedly mount a logic chip, an analog chip, a memory chip, etc. by stacking them while stabilizing power supply lines and ground lines of each chip. The semiconductor device has an intermediate substrate having a conductive portion and also having, on its one surface, an external connection terminal conducted to the conductive portion; and semiconductor chips each of which has connection portions, and which are mounted on both the surfaces of the intermediate substrate. At least two of the above semiconductor chips are electrically conducted to each other via the conductive portion of the intermediate substrate. At least one of a power supply line, a ground line, and a signal line of each of the semiconductor chips is connected to the conductive portion of the intermediate substrate via two or more, conducted to each other, of the connection portions.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: April 23, 2002
    Assignee: Sony Corporation
    Inventors: Kaneyoshi Takeshita, Toshiharu Yanagida
  • Patent number: 4974240
    Abstract: A charge-coupled device including a semiconductor substrate of given conductivity type, a buried channel formed on the substrate of different conductivity type than the substrate, an electrically floating diffusion formed in the substrate of different conductivity type than the substrate, and a plurality of electrodes insulating from the buried channel. The electrodes are responsive to applied voltages for supplying a signal charge through the buried channel to the floating diffusion. The charged-coupled device also includes a transistor responsive to a pulse voltage signal for periodically resetting the floating diffusion to a predetermined potential. The transistor comprises an enhancement type surface channel field effect transistor.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: November 27, 1990
    Assignee: Sony Corporation
    Inventors: Junya Suzuki, Kaneyoshi Takeshita
  • Patent number: 4920513
    Abstract: A semiconductor memory device having a number of memory cells. Each of the memory cells comprises a diode having a first electrode connected to a bit line. The diode has a second electrode connected at a point to one terminal of a storage capacitor, the other terminal of which is connected to a word line. A reset circuit is provided for resetting the point to a predetermined potential.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: April 24, 1990
    Assignee: Sony Corporation
    Inventors: Kaneyoshi Takeshita, Takeshi Matsushita