Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.

Abstract: Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.

Abstract: An active array color filter structure and a fabricating method therefor are provided, wherein the difference between the surface properties of lipophilicity and lipophobicity is utilized. When inks are coated on the active array substrate, ink at the lipophobic areas on the active array substrate will be naturally repelled, so that the color filter pixels formed on the active array substrate naturally have contact vias, which facilitates the electrical coupling of pixel electrodes and switch elements. Since there is no aligning or laminating process required for the color filter substrate and the active array substrate during fabrication, no aligning errors will occur. Also, as the pixel electrode can extend to cover above the corresponding switch element, the aggravation of the switch element is reduced.

Abstract: A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing generator, a first multiplexer and an initial value generator. The delay locked loop comprises a delay chain, a phase detector, a counter, and a decoder circuit. The delay locked loop delays an input clock signal to generate a first delay signal and several unit delay signals. The initial value generator receives the unit delay signals to generate an initial value used as an initial counting value of the delay locked loop to prevent harmonic lock. The delay locked loop controls the phase difference between the input clock signal and the first delay signal. The output clock signal of the clock recovery circuit is generated by the clock synthesizer circuit based on the input clock signal and the first delay signal.

Abstract: An apparatus for metal plating on a substrate with through-holes includes a chamber that the substrate is disposed inside the chamber to be divided into two sections. A pressure generator and a pressure controller are connected to this and correspond to two sides of the substrate respectively. The pressure generator is used for pumping a electrolyte flowed parallel to the surface of the substrate into the chamber. The pressure controller is used for channeling the electrolyte off the chamber and controlling the pressure differences between the two sides of the substrate. So that the electrolyte flowed parallel to the surface of the substrate is pumped by the pressure generator and it passes several through-holes to control the thickness of metal plating on the.substrate and inner walls of the through-holes.

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract: A method of fabricating a color organic electroluminescent display involves forming cathode electrodes on a substrate, and forming a first organic semiconductor layer having an electron-injection transporting property on the cathode electrodes. Solutions containing organic light-emitting material that can dissolve portions of the first organic semiconductor layer are patterned on the first organic semiconductor layer. Then, a solvent in the solutions is removed to form regions having second organic semiconductor layers and mixed organic semiconductor layers, wherein the second organic semiconductor layers are formed on the first organic semiconductor layer and are mostly composed of the organic light-emitting material, and the mixed organic semiconductor layers, composed of the organic light-emitting material and material constituting the first organic semiconductor layer, are embedded in the first organic semiconductor layer. Anode electrodes are formed over the first and second organic semiconductor layers.

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.

Abstract: In prior arts, additional pulse-width modulators and more costs are needed for increasing the current output. The invention provides a synchronized parallel running power converter. The power converter includes multiple power converters controlled by single-phase or double-phase pulse-width modulators. Each power converter includes a first pulse input port, a second pulse input port and a current output port. Each first pulse input ports are coupled, and each second pulse input ports are coupled also, so that each power converter is controlled by the same pulse signal and provide a same output current to be added as several times of current output.

Abstract: A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.

Abstract: In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such a seal vias, such that the difference in etch sensitivity between the created seal ring and the via holes is removed. All etch of the simultaneously etched features is completed at the same time, avoiding punch through of an underlying layer of etch stop material.

Abstract: A method for patching element defects by ink-jet printing includes steps of identifying all defects of the element by image analysis and obtaining an optimal ink-jet printing path of the ink-jet head. The ink-jet head repairs all defects of the element with the shortest distance along the optimal patching path. Moreover, the ink-jet head repairs all defects of the element in a stable manner so as to increase the yield rate.

Abstract: In prior arts, additional pulse-width modulators and more costs are needed for increasing the current output. The invention provides a synchronized parallel running power converter. The power converter includes multiple power converters controlled by single-phase or double-phase pulse-width modulators. Each power converter includes a first pulse input port, a second pulse input port and a current output port. Each first pulse input ports are coupled, and each second pulse input ports are coupled also, so that each power converter is controlled by the same pulse signal and provide a same output current to be added as several times of current output.

Abstract: A semiconductor package seal ring including a plurality of insulating layers, a plurality of conductive runners each embedded in one of the insulating layers, and a plurality of conductive posts each contacting one of the conductive runners and extending through at least one of the insulating layers and at least partially through an opening in another one of the conductive runners.

Abstract: A semiconductor package seal ring including a plurality of insulating layers, a plurality of conductive runners each embedded in one of the insulating layers, and a plurality of conductive posts each contacting one of the conductive runners and extending through at least one of the insulating layers and at least partially through an opening in another one of the conductive runners.

Abstract: A multiple layer metal interconnect process provides for both good electrical properties and good mechanical properties by using a first extremely low k dielectric material at the lower level metal layers, a second extremely low k dielectric material at the middle level metal layers, and a low k dielectric material at the upper level metal layers.

Abstract: A method of treating atherosclerosis is disclosed wherein nicotinic acid or another nicotinic acid receptor agonist is administered to the patient in combination with a DP receptor antagonist. The DP receptor antagonist is administered to reduce, prevent or eliminate flushing that may otherwise occur.

Abstract: A method of integrated circuit fabrication includes first forming at least one via in an insulting layer, and thereafter forming at least one trench-like structure separately. After a via is formed in an insulating layer, a layer of resist material is formed on the surface of the insulting layer and substantially filled the via. This step is followed by patterning at least one trench-like structure on the resist layer, and the trench-like structure is etched to the desired level. In some other embodiments, at least one trench-like structure is formed before at least one via is formed. An integrated circuit is manufactured by the aforementioned methods.

Abstract: An apparatus and process for automatically, repetitively sampling blood from conscious animals. The apparatus can simultaneously extract blood from a number of conscious, catherized animals at programmable time intervals. The apparatus is characterized as a system of computer controlled valves and pumps connected by tubing filled with saline solution to a catherized animal. Blood samples are collected via a cannula from the animal and placed in a fraction collector for analyses.

Abstract: A method of fabrication used for semiconductor integrated circuit devices to define a thin copper fuse at a top via opening, in a partial etch, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation. Some advantages of the method are: (a) avoids copper fuse contact to low dielectric material, which is subject to the thermal shock of laser ablation, (b) increases insulating material thickness over the fuse using better thickness control, and most importantly, (c) reduces the copper fuse thickness, for easy laser ablation of the copper fuse, and finally, (d) uses USG, undoped silicate glass to avoid direct contact with low dielectric constant materials.