Patents by Inventor Kang Cheng

Kang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8698175
    Abstract: The present invention relates to a light-emitting diode (LED). The LED comprises an LED die, one or more metal pads, and a fluorescent layer. The characteristics of the present invention include that the metals pads are left exposed for the convenience of subsequent wiring and packaging processes. In addition, the LED provided by the present invention is a single light-mixing chip, which can be packaged directly without the need of coating fluorescent powders on the packaging glue. Because the fluorescent layer and the packaging glue are not processed simultaneously and are of different materials, the stress problem in the packaged LED can be reduced effectively.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: April 15, 2014
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Wei-Kang Cheng, Jia-Lin Li, Shyi-Ming Pan, Kuo-Chin Huang
  • Publication number: 20140092499
    Abstract: A display panel driver circuit includes multiple drivers adapted for cooperatively driving a display panel and each operable under a protection mode, and an overheat protection device including multiple protection circuits, each of which controls a respective one of the drivers to operate under the protection mode in response to receipt of an enable signal, an interface circuit which transmits the enable signal to each of the protection circuits in response to receipt of a warning signal, and multiple temperature detection circuits, each of which is able to detect a temperature associated with a respective one of the drivers, and outputs the warning signal to the interface circuit based on the temperature thus detected.
    Type: Application
    Filed: March 11, 2013
    Publication date: April 3, 2014
    Applicant: ILI TECHNOLOGY CORPORATION
    Inventors: Chih-Kang Cheng, Feng-Hsiang Huang
  • Patent number: 8658443
    Abstract: A method for manufacturing light emitting device is provided. Firstly, provide a substrate. Then arrange a light emitting unit on the substrate. Next form at least one electrode and arrange at least one protective layer on the electrode. The protective layer is to prevent a phosphor layer following formed on the light emitting unit from covering the electrode. After forming the phosphor layer, flatten the phosphor layer and the protective layer. A part of the phosphor layer over the protective layer is removed. Thus the electrode is not affected by the phosphor layer and conductivity of the electrode is improved to resolve phosphor thickness and uniformity problems of the light emitting device. Therefore, the thickness of the light emitting device with LED is effectively reduced and stability of white color temperature control is significantly improved.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: February 25, 2014
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Wei-Kang Cheng, Yu-Chih Lin, Han-Zhong Liao, Yi-Sheng Ting, Shyi-Ming Pan
  • Publication number: 20140018232
    Abstract: The invention relates to a catalyst for selective synthesis of high-quality gasoline fractions from syngas and the preparation method of the catalyst. This catalyst consists of cobalt, a promoter and molecular sieve, wherein cobalt is presented in an amount of 1-30%, the promoter is represented in an amount of 0.01-5% and the balance is molecular sieve based on the weight of the catalyst. This catalyst provides superior selectivity for C5-C11 isoparaffins and relatively lower selectivity for wax-type hydrocarbons with more than 20 carbon atoms. Thereof, this catalyst can be used for the synthesis of high-quality gasoline and is good at preventing catalyst coking. Besides, the invention provides a preparation method of the catalyst.
    Type: Application
    Filed: April 2, 2011
    Publication date: January 16, 2014
    Inventors: Ye Wang, Jincan Kang, Lei Zhang, Qinghong Zhang, Kang Cheng, Qingge Zhai, Jiansheng Ding, Weiqi Hua, Yinchuan Lou
  • Publication number: 20130322081
    Abstract: A light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED chips are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED chips. Each of the LED chips includes a first electrode and a second electrode. Light emitted from at least one of the LED chips passes through the transparent substrate and emerges from the second main surface. An illumination device includes the light emitting element and a supporting base. The light emitting element is disposed on the supporting base, and an angle is formed between the light emitting element and the supporting base.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 5, 2013
    Inventors: Shyi-Ming Pan, Wei-Kang Cheng, Chih-Shu Huang, Chen-Hong Lee, Shih-Yu Yeh, Chi-Chih Pu, Cheng-Kuang Yang, Shih-Chieh Tang, Siang-Fu Hong, Tzu-Hsiang Wang
  • Publication number: 20130320363
    Abstract: A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 5, 2013
    Applicant: Formosa Epitaxy Incorporation
    Inventors: Shyi-Ming Pan, Wei-Kang Cheng, Chih-Shu Huang, Chen-Hong Lee, Shih-Yu Yeh, Chi-Chih Pu, Cheng-Kuang Yang, Shih-Chieh Tang, Siang-Fu Hong, Tzu-Hsiang Wang
  • Publication number: 20130320373
    Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 5, 2013
    Applicant: FORMOSA EPITAXY INCORPORATION
    Inventors: CHI-CHIH PU, CHEN-HONG LEE, SHIH-YU YEH, WEI-KANG CHENG, SHYI-MING PAN, SIANG-FU HONG, CHIH-SHU HUANG, TZU-HSIANG WANG, SHIH-CHIEH TANG, CHENG-KUANG YANG
  • Publication number: 20130293451
    Abstract: A liquid crystal display apparatus includes a liquid crystal panel and a panel driving device. The panel driving device includes a timing control circuit, a gate driving circuit, and a source driving circuit. The source driving circuit includes a low voltage differential signal (LVDS) receiver, a driving voltage generator, and a controller. The LVDS receiver includes a plurality of receive circuits and a power saving control circuit. Each of the receive circuit performs level conversion upon a data LVDS to generate a logic signal, and operates in a selected one of a normal energy consuming mode and a power saving mode. The power saving control circuit controls the receive circuits to operate in the power saving mode when the power saving control circuit does not receive a power adjustment signal from the controller.
    Type: Application
    Filed: March 13, 2013
    Publication date: November 7, 2013
    Applicant: ILI TECHNOLOGY CORPORATION
    Inventors: Sung-Yau YEH, Chin-Kang CHENG, Bing-Hung CHEN
  • Patent number: 8541264
    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8450161
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
  • Publication number: 20130104956
    Abstract: A solar cell module includes multiple solar cells connected in series through wiring units. Each solar cell comprises an electrode unit disposed on a photoelectric conversion unit converting solar energy into electrical energy, and including multiple finger electrodes. At least one finger electrode has a first conducting section connected to a bus bar electrode, and a second conducting section disposed on one side of the first conducting section, extending away from the bus bar electrode and having a thickness greater than that of each of the first conducting section and the bus bar electrode.
    Type: Application
    Filed: June 11, 2012
    Publication date: May 2, 2013
    Applicant: MOTECH INDUSTRIES INC.
    Inventors: Ming-Tzu Chou, Chien-Wen Chen, Ching-Hao Tu, Chih-Chiang Huang, Kang-Cheng Lin
  • Publication number: 20130075936
    Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Jianmin Fang, Xia Feng, Kang Cheng
  • Publication number: 20130009096
    Abstract: An oxynitride phosphor and a method of manufacturing the same are revealed. The formula of the oxynitride phosphor is Ba3-x-ySi6O12N2:Cey, Eux (0?x?1, 0?y?1). Europium (Eu) and cerium (Ce) are luminescent centers. The oxynitride phosphor is synthesized by solid-state reaction. The oxynitride phosphor is excited by vacuum ultraviolet light with a wavelength range of 130 nm to 300 nm or ultraviolet to visible light with a wavelength range of 350 nm to 550 nm. The emission wavelength of the oxynitride phosphor is ranging from 400 nm to 700 nm. Thus the oxynitride phosphor can be applied to plasma display panels and ultraviolet (UV) excitation sources. The energy transfer occurs between Ce and Eu of the oxynitride phosphor and the oxynitride phosphor has a blue light emission peak and a green light emission peak. Thus color rendering index of the oxynitride phosphor is improved.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 10, 2013
    Applicant: FORMOSA EPITAXY INCORPORATION
    Inventors: CHENG-I CHU, RU-SHI LIU, YU-CHIH LIN, CHEN-HONG LEE, WEI-KANG CHENG, YI-SHENG TING, SHYI-MING PAN
  • Publication number: 20130009097
    Abstract: An oxynitride phosphor and a method of manufacturing the same are revealed. The formula of the oxynitride phosphor is Ba3-xSi6O12N2: Yx (0?x?1). Y is praseodymium (Pr) or terbium (Tb) used as a luminescent center. The oxynitride phosphor is synthesized by solid-state reaction. The oxynitride phosphor is excited by vacuum ultraviolet light with a wavelength range of 130 nm to 300 nm or ultraviolet to visible light with a wavelength range of 300 nm to 550 nm to emit light with a wavelength range of 400 nm to 700 nm. Moreover, the full-width at half-maximum of the emission spectrum is smaller than 30 nm. Thus the oxynitride phosphor is suitable for applications of backlights, plasma display panels and ultraviolet excitation. The oxynitride phosphor has higher application value.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 10, 2013
    Applicant: FORMOSA EPITAXY INCORPORATION
    Inventors: CHENG-I CHU, RU-SHI LIU, YU-CHIH LIN, CHEN-HONG LEE, WEI-KANG CHENG, YI-SHENG TING, SHYI-MING PAN
  • Publication number: 20130009095
    Abstract: A method of manufacturing an oxynitride phosphor is revealed. A precursor is sintered under 0.1-1000 MPa nitrogen pressure for synthesis of an oxynitride phosphor. The general formula of the oxynitride phosphors is MxAyBzOuNv (0.00001?x?5; 0.00001?y?3; 0.00001?z?6; 0.00001?u?12; 0.00001?v?12). M is an activator or a mixture of activators. A is a bivalent element or a mixture of bivalent elements. B is a trivalent element, a tetravalent element, a mixture of trivalent elements or a mixture of tetravalent elements. O is a univalent element, a bivalent element, a mixture of univalent elements, or a mixture of bivalent elements. N is a univalent element, a bivalent element, a trivalent element, a mixture of univalent elements, a mixture of bivalent elements, or a mixture of trivalent elements. Thus pure phosphor can be mass-produced.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 10, 2013
    Applicant: FORMOSA EPITAXY INCORPORATION
    Inventors: CHENG-I CHU, RU-SHI LIU, YU-CHIH LIN, CHEN-HONG LEE, WEI-KANG CHENG, YI-SHENG TING, SHYI-MING PAN
  • Publication number: 20120273024
    Abstract: A solar cell module includes lower and upper substrates that are spaced apart from each other, a plurality of spaced apart solar cells, a plurality of gratings, and a light-transmissive encapsulant disposed between the lower and upper substrates to encapsulate the solar cells and the gratings. Each of the gratings has a grating center, and four reflecting regions formed around the grating center. Each of the reflecting regions has a light entrance face that has a plurality of valleys and peaks. The valleys and peaks alternate with each other along a direction from the grating center to a corresponding one of the corners of a corresponding one of the four adjacent solar cells.
    Type: Application
    Filed: September 22, 2011
    Publication date: November 1, 2012
    Applicant: MOTECH INDUSTRIES INC.,
    Inventors: Chu-Jung Ko, Kang-Cheng LIN
  • Publication number: 20120276732
    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Publication number: 20120225529
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Application
    Filed: May 7, 2012
    Publication date: September 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
  • Patent number: 8242576
    Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8193586
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: June 5, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen