Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

Abstract: A chip electronic component includes a magnetic body including magnetic metal powder particles, an internal coil unit embedded in the magnetic body, and a cover unit disposed on at least one of upper and lower surfaces of the magnetic body and including a magnetic metal plate. The magnetic metal plate is cracked and includes a plurality of metal fragments.

Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 ?m to 70 ?m.

Abstract: A multilayer ceramic electronic component includes: a body part including dielectric layers and internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and external electrodes disposed on an outer surface of the body part and electrically connected to the internal electrodes. The dielectric layer includes grains including: a semiconductive or conductive grain core region containing a base material represented by ABO3, where A is at least one of Ba, Sr, and Ca, and B is at least one of Ti, Zr, and Hf, and a doping material including a rare earth element; and an insulating grain shell region enclosing the grain core region.

Abstract: A method of manufacturing a coil device and the coil device includes a base layer and a coil pattern formed on a surface of the base layer. The method of manufacturing a coil device includes forming a seed layer of a coil by bonding a copper foil to a base layer, etching to remove a portion of the copper foil, and plating a plating layer on the seed layer.

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

Abstract: The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface; a first capacitor disposed adjacently to the semiconductor chip; an encapsulant at least partially encapsulating the first connection member and the semiconductor chip; a first connection member disposed on the encapsulant, the first capacitor, and the semiconductor chip, and a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed, wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the connection pad through a common power wiring of the redistribution layer.

Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 ?m to 70 ?m.

Abstract: A multilayer ceramic electronic component includes: a body part including dielectric layers and internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and external electrodes disposed on an outer surface of the body part and electrically connected to the internal electrodes. The dielectric layer includes grains including: a semiconductive or conductive grain core region containing a base material represented by ABO3, where A is at least one of Ba, Sr, and Ca, and B is at least one of Ti, Zr, and Hf, and a doping material including a rare earth element; and an insulating grain shell region enclosing the grain core region.

Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

Abstract: An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.

Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Abstract: An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.

Abstract: A wireless power receiving device includes a first coil partially disposed in an outer region and configured to transmit and/or receive data; and a second coil disposed inwardly of an inner boundary line of the outer region and configured to receive wirelessly transmitted power, wherein a center defined by an inner boundary line and a center defined by an outer boundary line of the second coil are different from each other.

Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.

Abstract: There is provided a thin film-type coil component having a size equal to or less than 0806 and including a ceramic main body, external electrodes including a plurality of first external electrodes formed on one surface of the ceramic main body and a plurality of second external electrodes formed on the other surface facing one surface of the ceramic main body, and a coil unit including a plurality of coil layers stacked in the ceramic main body, thereby obtaining low direct current (DC) resistance.