Abstract: An RF switch is provided. In the RF switch, a T-junction slot line has a horizontal slot line and a vertical slot line. An open-end circuit is provided at each end portion of the horizontal and vertical slot lines. A first transmission line delivers signals from and to one portion of the horizontal slot line, and a second transmission line delivers signals from and to the other portion of the horizontal slot line. A third transmission line delivers signals from and to the vertical slot line. A switching circuit selectively switches the signal path of the one or the other portion of the horizontal slot line to the vertical slot line according to an external switching control signal.

Abstract: Method for fabricating a semiconductor device in which a by-product of etching is deposited on a photoresist film for using as a mask. The method for fabricating a semiconductor device includes the steps of depositing a polysilicon, and a bottom anti-refection coating on an entire surface of a substrate in succession, forming a photoresist film pattern on a predetermined portion of the bottom anti-refection coating, etching the bottom anti-refection coating by using the photoresist film pattern to deposit by-product of the etching on sidewalls of the photoresist pattern to form spacers, and etching the polysilicon by using the photoresist film pattern and the spacers, to form a line.

Abstract: A method of performing communication in a mobile terminal includes performing data communication, determining whether a release order message received while data communication is being performed indicates that there is a voice communication request, allocating a traffic channel for voice communication if the release order message indicates that there is a voice communication request, receiving the voice communication request through the traffic channel, and displaying the voice communication request.

Abstract: A method for forming a contact hole for a dual damascene interconnection in a semiconductor device. A via hole is formed to expose an etch stop film on a lower metal film through an intermetal insulating film. The via hole is filled with a sacrificial film. A bottom antireflective coating film and a mask pattern are formed on the intermetal insulating film and the sacrificial film. An etching process is performed to form a trench to expose a portion of a surface of the intermetal insulating film and a top surface of the sacrificial film. A post etch treatment is performed to remove the sacrificial film, using the mask pattern as an etching mask. The exposed etch stop film is removed to expose a portion of a surface of the lower metal film. A passivation process is performed for the exposed surface of the lower metal film.

Abstract: A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; forming a hard mask on the polysilicon layer; depositing photoresist on the hard mask and patterning the hard mask by using the photoresist; and etching the polysilicon layer using the pattern embodied by the hard mask. By fabricating a gate oxide with a finer linewidth using a hard mask and existing equipment, the present invention can control the linewidth required in each product by using an etching process, and, therefore, has advantages such as expandability of process, extension of generality, and maximization of productivity in the production line.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device. An etch stop film and an intermetal insulating film are formed sequentially on a lower metal film. A via hole is formed to expose a portion of a surface of the etch stop film through the intermetal insulating film. A sacrificial film is formed to fill the via hole. Portions of the intermetal insulating film and the sacrificial film are removed to form a trench. The sacrificial film is removed to expose the portion of the surface of the etch stop film. A plasma etching process is performed at a predetermined temperature using an etching gas to remove the exposed portion of the etch stop film and to prevent or suppress generation of a polymer. A diffusion barrier film is formed within the trench and the via hole such that the diffusion barrier contacts the lower metal film. An upper metal film is formed on the diffusion barrier.

Abstract: A method for forming a contact hole for a dual damascene interconnection in a semiconductor device. A via hole is formed to expose an etch stop film on a lower metal film through an intermetal insulating film. The via hole is filled with a sacrificial film. A bottom antireflective coating film and a mask pattern are formed on the intermetal insulating film and the sacrificial film. An etching process is performed to form a trench to expose a portion of a surface of the intermetal insulating film and a top surface of the sacrificial film. A post etch treatment is performed to remove the sacrificial film, using the mask pattern as an etching mask. The exposed etch stop film is removed to expose a portion of a surface of the lower metal film. A passivation process is performed for the exposed surface of the lower metal film.

Abstract: A method for forming a dual damascene interconnection in a semiconductor device. An etch stop film and an intermetal insulating film are formed sequentially on a lower metal film. A via hole is formed to expose a portion of a surface of the etch stop film through the intermetal insulating film. A sacrificial film is formed to fill the via hole. Portions of the intermetal insulating film and the sacrificial film are removed to form a trench. The sacrificial film is removed to expose the portion of the surface of the etch stop film. A plasma etching process is performed at a predetermined temperature using an etching gas to remove the exposed portion of the etch stop film and to prevent or suppress generation of a polymer. A diffusion barrier film is formed within the trench and the via hole such that the diffusion barrier contacts the lower metal film. An upper metal film is formed on the diffusion barrier.

Abstract: A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; forming a hard mask on the polysilicon layer; depositing photoresist on the hard mask and patterning the hard mask by using the photoresist; and etching the polysilicon layer using the pattern embodied by the hard mask. By fabricating a gate oxide with a finer linewidth using a hard mask and existing equipment, the present invention can control the linewidth required in each product by using an etching process, and, therefore, has advantages such as expandability of process, extension of generality, and maximization of productivity in the production line.

Abstract: The present invention is directed to a method for fabricating a metal line of a semiconductor device. The method comprises the steps of forming an insulation layer, a metal layer and an organic anti-reflection coating in order on a semiconductor substrate on which devices or lower lines are formed, forming a photoresist pattern having an opening of certain width on the organic anti-reflection coating, forming a buffer layer of certain thickness on the photoresist pattern, and selectively removing the metal layer at a lower side of the opening by performing a dry etching process.

Abstract: A method for forming a fine pattern, e.g., for forming the storage electrodes of the capacitors of the memory cells of semiconductor memory devices, which includes the steps of depositing a mask layer on the layer to be patterned, depositing a photoresist layer on the mask layer, patterning the photoresist layer, to thereby form a photoresist pattern, anisotropically etching the mask layer, using the photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of the photoresist pattern and the mask layer pattern, and, etching the layer to be patterned using the composite layer and the etch by-products as an etching mask, to thereby form a fine pattern. The mask layer is made of a material, e.g., a high-temperature oxide, having different physical properties than that of the photoresist. Further, the anisotropic etching process is preferably carried out by means of a plasma etching process using a mixture of CF.