Abstract: Provided is a wavelength tunable light source including a semiconductor optical amplifier, a beam steering unit or a beam deflector, and a concave diffraction grating integrated therein. The wavelength tunable light source can be easily implemented since locations to which a beam is diffracted by the concave diffraction grating and at which portions of the beam with different wavelengths have constructive interference form a straight line, not a Rowland circle. Furthermore, wavelength tuning and optical coupling characteristics of the wavelength tunable light source are excellent. Since both single integration and hybrid integration are possible for the wavelength tunable light source, the wavelength tunable light source exhibits superior operating characteristics and high reliability.

Abstract: An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output of each converter. Each converter assesses the magnitude of its input voltage, and outputs a signal that is asserted at a time in inverse proportion to the magnitude of the input voltage. In one embodiment, producing the output signal at the asserted time comprises using the input voltage to gate a transistor whose discharge rate dictates the timing of the output signal. The two output signals arrive at an arbiter circuit whose function is to determine which output arrived at the arbiter first, as is indicative of the higher magnitude input voltage, and to set the output of the comparator accordingly.

Abstract: A separator sheet for manufacturing an electric double layer capacitor, and a method for manufacturing the electric double layer capacitor using the same, are provided. According to an embodiment, the separator sheet for manufacturing the electric double layer capacitor comprises: a plurality of separators; and a resin film holding the plurality of separators, wherein the separators are disposed in the resin film at a predetermined interval.

Abstract: The present invention relates to a prism sheet having a side which is perpendicular to the normal of a light guiding plate. The prism sheet includes a prism sheet base film and a plurality of linearly aligned prisms. The prisms are formed on one side of the prism sheet base film. Here, one side of each prism is perpendicular to the prism sheet base film. The prism sheet condenses a light outputted from a light guiding plate using its internal total reflection, and so the efficiency of the light is enhanced.

Abstract: The present invention relates to a backlight unit having a polarization film for performing the function of a reflective polarization film. The backlight unit includes a light source, an optical film and a polarization film. The light source emits a light having a certain wavelength. The optical film is located proximate to the light source to transmit the light outputted from the light guiding plate in a certain direction. The polarization film is located proximate to the optical film. Here, the polarization film has a UV curing resin and lines disposed on the UV curing resin, and polarize the light transmitted from the optical film. The backlight unit manufactures the polarization film by using UV curing resin and metal substance, and thus the manufacture period of the polarization film may be reduced. Accordingly, the polarization film may be manufactured in great quantities.

Abstract: A device and system having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.

Abstract: An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further includes delaying the clock input by an alignment magnitude to generate a first aligned phase signal and delaying each of the N delay taps by fractional amounts of the alignment magnitude to generate N phase aligned signals. A feedback loop is closed by a phase comparison between the first aligned phase signal and the cycle delay signal. The phase comparison result is used to adjust the cycle delay magnitude, which adjusts delays of the cycle delay signal and the N delay taps, and adjust the alignment magnitude, which adjust delays of the first aligned phase signal and the N phase aligned signals.

Abstract: A liquid crystal spraying apparatus is provided. In the apparatus, a liquid crystal vessel stores liquid crystal. A liquid crystal nozzle sprays the stored liquid crystal in the form of fine particles. A liquid crystal supplier supplies the stored liquid crystal to the liquid crystal nozzle. A gas supplier supplies gas causing the supplied liquid crystal to be sprayed in the form of fine particles. A gas tank supplies the gas to the gas supplier.

Abstract: A judder detection apparatus, a de-interlacing apparatus using the judder detection apparatus, and a de-interlacing method. The judder detection apparatus includes a judder detector to detect whether a detected pattern that is similar to a judder pattern occurs using predetermined pixel values of even and odd fields sequentially input, a pattern detector to detect whether an input image has a uniform pixel value in every other line of the even and odd fields and whether consecutive lines of the even and odd fields have a blind pattern having a difference from the uniform pixel that is greater than or equal to a threshold value, and a determiner to determine whether the detected pattern that is similar to the judder pattern is a judder based on whether the blind pattern is detected.

Abstract: Provided is an integrated semiconductor light source using locking characteristic by an external light injection, including: an active region controlling an optical gain and an optical output by current injection; and a passive region having a structure integrated with the active region and moving a cavity mode by current injection or voltage application to lock injection light.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: Provided is a method of fabricating a ridge type waveguide integrated semiconductor optical device.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Provided is an optical deflector for deflecting radiation beams. The optical deflector includes: a peripheral region having a first effective refractive index; and a deflection pattern region having a predetermined shape and a second effective refractive index, wherein the second effective refractive index differs from the first effective refractive index. Here, due to the deflection pattern region having the predetermined shape, the radiation beams are deflected in a direction starting from a certain point. By using the optical deflector, the locus of a light source can be designed in one of various forms, such as a straight line, a circle, an ellipse, or a parabola.

Abstract: A device and system having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The output of the fine delay block may be implemented to control a coarse delay block in a delay lock loop.

Abstract: Provided is a tunable external cavity laser diode using a variable optical deflector wherein the variable optical deflector, in which a refractive index varies according to an electrical signal, is arranged in a triangular shape between a concave diffraction grating and a reflective mirror. Since a resonant frequency is changed using the electrical signal rather than the mechanical movement, the stable operation and continuous high-speed tenability may be enabled. In addition, when the tunable external cavity laser diode according to the present invention is implemented in an InP/InGaAsP/InP slab waveguide, a variable time determined by the carrier lifetime may be reduced to several nanoseconds or less, the miniaturization is enabled, and the manufacturing costs are significantly reduced due to the process simplification.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.