Abstract: Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer that switches polarization in response to an electric field from the applied voltage and a narrow channel conductor of a spin-orbit coupling (SOC) material on the ME layer. One or more sources and one or more drains, each optionally formed of ferromagnetic material, are provided on the SOC material.

Abstract: Systems and methods in accordance with embodiments of the invention implement select devices constructed from 2D materials. In one embodiment, a crossbar memory system includes: a first set of connection lines; a second set of connection lines; and an array of memory cells, each memory cell including: a select device; and a memory device; where each memory cell is coupled to a unique combination of: at least one connection line from the first set of connection lines, and at least one connection line from the second set of connection lines; and where at least one select device includes a 2D material.

Abstract: A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.

Abstract: A device includes a substrate with a tunnel barrier disposed on active region defined on the substrate, a monolayer of graphene disposed on the tunnel barrier, a dielectric material disposed on the graphene, and an electrode disposed over a region of the dielectric material. A first voltage is applied across the electrode and the graphene to adjust a Fermi level within the graphene to a Fermi level position within the valence band of the graphene based upon a predetermined emission wavelength. A current is injected into the graphene's conduction band to cause the graphene to emit a broadband hot electron luminescence (HEL) spectrum of photons peaked at the predetermined emission wavelength. The device may be configured as a vertical-tunneling light-emitting hot-electron transistor. The broadband HEL photon emission spectrum emanating from the graphene may be voltage-tunable within the electromagnetic spectrum from UV to THz.

Abstract: Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer that switches polarization in response to an electric field from the applied voltage and a narrow channel conductor of a spin-orbit coupling (SOC) material on the ME layer. One or more sources and one or more drains, each optionally formed of ferromagnetic material, are provided on the SOC material.

Abstract: Flexible, conductive, graphene-polymer nanocomposites incorporating doped graphene and conductive polymer materials in a layered structure and tunable methods of fabrication are provided. The layered graphene-polymer nanocomposites exhibit resistance quenching by suppressing defect induced carrier scattering in graphene while keeping the optical transmittance greater than 90%, which is essential for many optoelectronic applications. Nanocomposites also demonstrate high mobility and carrier density compared to known TCF materials as well as very low sheet resistance with flexibility of more than ±90 degrees of bending angle. The methods employ layer-by-layer mixed chemical doping strategies that incorporate different doping species to enhance electrical and optical properties individually. The synthesis of the graphene-polymer nanocomposite may be conducted by chemical processes to provide mass production capabilities.

Abstract: A periodically-rippled patch antenna structure with metal coated trenches only along one in-plane direction or in two perpendicular in-plane directions on a dielectric substrate and ground plane and methods of fabricating the antenna radiating elements are provided. An optional layer of oxide or nitride can be placed between the substrate and metal layers as an insulation layer. This use of trenches allows for miniaturization of the patch antenna as well as dual-band degeneracy. When a square 1D rippled patch antenna is excited by a microstrip line connected along the ripples, the effective length is longer than with a line orthogonal to the ripples enabling dual mode degeneracy and antennas working at two distinct frequencies of operation.

Abstract: A method for fabricating nanoscale patterned oxide substrates and devices incorporating the substrates are provided. Highly periodic or non-periodic sinusoidal patterns and other fine oxide patterns are formed on the surface of a suitable base such as silicon. Fine oxide surface patterns are created with photolithography, etching and three different oxide formation events. Thin layers of conductor materials including graphene and metals can be applied to the oxide surface patterns of the substrate and conform to the pattern allowing morphology and physical properties the conductor layer to be tuned. Control over device characteristics is demonstrated by varying the dimensions, strain, orientation, wavelength and amplitude of graphene sheet corrugations. A patch antenna device with a periodic sinusoidal graphene sheet on a silicon oxide substrate mounted to a ground plane was demonstrated.

Abstract: A fast and low-power sense amplifier and writing circuit for high-speed Magnetic RAM (MRAM) which provides the long retention times and endurance of magnetic tunnel junction (MTJ) cells, while providing faster access speeds, verified writes, and an increased sensing margin. A high-speed and low-power pre-read and write sense amplifier (PWSA) provide VCMA effect precessional switching of MTJ cells which include pre-read and comparison steps which reduce power consumption. An embodiment of the PWSA circuit is described with write and pre-charge circuit, S and D latches, comparison circuit, and a differential amplifier and control circuit.

Abstract: A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.

Abstract: A magnetic memory bit structure using voltage-controlled magnetic anisotropy (VCMA) for switching the state of at least one magnetic free layer (FL) is configured for inducing strain to achieve very large VCMA coefficients, toward reducing the electric field potential and/or voltage required for switching the state of the magnetic free layer (FL). The disclosed apparatus and method increases voltage-controlled magnetic anisotropy (VCMA) efficiency, which is the change of interfacial magnetic anisotropy energy per unit electric field, thus exploiting strain engineering in designing next generation MeRAM devices which operate more efficiently with lower switching thresholds.

Abstract: A fast and low-power sense amplifier and writing circuit for high-speed Magnetic RAM (MRAM) which provides the long retention times and endurance of magnetic tunnel junction (MTJ) cells, while providing faster access speeds, verified writes, and an increased sensing margin. A high-speed and low-power pre-read and write sense amplifier (PWSA) provide VCMA effect precessional switching of MTJ cells which include pre-read and comparison steps which reduce power consumption. An embodiment of the PWSA circuit is described with write and pre-charge circuit, S and D latches, comparison circuit, and a differential amplifier and control circuit.

Abstract: Epitaxial growth of gallium arsenide (GaAs) on a semiconductor material (e.g., Si) using quasi-van der Waals Epitaxy (QvdWE). Prior to GaAs growth a buffer layer (e.g., graphene) is deposited which relieves lattice mismatch/thermal expansion. The low energy of the graphene surface and the GaAs/graphene interface is overcome through an optimized growth technique to obtain an atomically smooth low-temperature GaAs nucleation layer. The disclosure can be applied to optimize epitaxial thin film growth of other materials, (e.g., III-V semiconductors, such as InP, GaSb) on Si using van der Waals buffer layers such as graphene.

Abstract: A nanoscale tunnel magneto-resistance (TMR) sensor comprising an in-plane-magnetized reference layer and a free layer comprising interfacial perpendicular anisotropy, wherein the free layer comprises a sensing layer for sensing resistance as a function of applied magnetic field and is tunable to vary the direction of the sensing layer magnetization to be in-plane, canted, or out-of-plane.

Abstract: Embodiments of the technology implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between the fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series.

Abstract: Embodiments of the technology implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between said fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series.

Abstract: Embodiments of the technology implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between said fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series.

Abstract: Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics.

Abstract: A basic Spin-Orbit-Torque (SOT) structure with lateral structural asymmetry is provided that produces a new spin-orbit torque, resulting in zero-field current-induced switching of perpendicular magnetization. More complex structures can also be produced incorporating the basic structure of a ferromagnetic layer with a heavy non-magnetic metal layer having strong spin-orbit coupling on one side, and an insulator layer on the other side with a structural mirror asymmetry along the in-plane direction. The lateral structural asymmetry and new spin-orbit torque, in effect, replaces the role of the external in-plane magnetic field. The direction of switching is determined by the combination of the direction of applied current and the direction of symmetry breaking in the device.

Abstract: Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics.