Abstract: The present invention discloses a method of personalizing icons on an electronic communication product, comprising the steps of installing an image processing program into an electronic communication product, executing the image processing program to edit any icon on the screen of the electronic communication product; connecting an input device (such as a keyboard or a light pen) to the electronic communication product to click on the icon; and selecting the type of desired effect on the original icon; and displaying the edited icon on the screen of the electronic communication product. Such method is applicable for an electronic communication platform of handheld computers such as a handset and a personal digital assistance (PDA).

Abstract: This invention discloses a method of protecting copyright of a digital video work by using a digital password technology and a digital watermark technology to prevent the unauthorized use of a digital video work. Such method adds a password into two color matrixes of such video work in advance, so that when such video work is published on the Internet, it can be played by a specified player. As long as a user enters the correct password into the specified player, a full visual effect of such video work can be obtained. If other players are used to play such video work, only partial gray-scale visual effect can be obtained. Users must request or buy a specific player and a password from the distributor of such video work to play the complete information to prevent piracy.

Abstract: A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of a particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs achievable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field.

Abstract: The present invention discloses an input equipment with a sensed movement feedback, which comprises a pressure sensor pad having a through hole at the center, a rolling ball disposed in the through hole with part of the rolling ball exposed and protruded therefrom, and at least one driver contacting with the surface of the rolling ball. The sensor pad will produce a signal according to a pressing force exerting thereon and transmit the signal to a control circuit of the input equipment, enabling the control circuit to produce a rolling signal for activating the driver to move the rolling ball in a direction proportion to the pressing force. Thus, the user can sense the direction and speed of the cursor movement on the screen from sensing the rolling movement of the rolling ball.

Abstract: A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field.

Abstract: A new type of pipeline, generally referred to as a logical pipeline is disclosed. A logical pipeline generaly includes a set of hardware based pipeline stages that exchange data through a common pipeline memory, instead of only through intermediate fixed physical buffers. Thus, operational data is retrieved and stored by each stage using a single memory, and this permits flexible and programmable forms of pipelines that can be adapted as needed in response to a desired computation task. A common pipeline clock initiates processing of the data. Another variation is disclosed in the form of a logical “hybrid” pipeline, consisting of both software and hardware based pipeline stages, that are used to perform a set of computations in an interleaved fashion. In this manner, a data item can be handled first by a hardware pipeline stage, followed immediately by a software pipeline stage, etc.

Abstract: A digital communications link, protocol and related circuits are provided which achieve a scaleable performance rate through a combination of clock scaling and/or variable frame sizing. The system is used within a personal computer, thus allowing the latter to be interoperable with any number of different communications protocols, including xDSL based transmission standards, and to set up communications links of varying capacity and performance.

Abstract: A system for generating a phase detection signal, for recovering a transmitter clock, and for sampling data in a received signal. A stream of digital samples is collected from the received signal at a sampling phase and autocorrelation based on the digital samples is used to derive the phase detection signal. The phase detection signal is then further usable to recover the transmitter clock by generating a reference signal and locking it with the received signal. The recovered transmitter clock is yet further usable to sample data in the received signal. Optionally, another autocorrelation based on the digital samples may be used to also derive a phase for optimally sampling data in a received signal.

Abstract: A system for selecting a sampling phase for recovering data from a received signal that has been generated based on a transmitter clock. A sampling clock is provided, typically by recovering the transmitter clock. Digital samples of the received signal are then obtained for each of a set of phase delays of the sampling clock and data values are calculated based on autocorrelation of the digital samples. One phase delay is then selected as the sampling phase for the received signal based on said data values. Optionally, this system may be used with a clock recovery system that also employs autocorrelation based on digital samples of the received signal. This permits clock recovery and selecting an optimum sampling phase without having otherwise pre-determined or closely approximated the transmitter clock.

Abstract: A broadband digital communications link, protocol and related I/O circuits are provided which use an embedded control channel and a frame structure for transferring control information between different sections of a broadband system, including within a personal computer. A dedicated bus within the personal computer is used to support a variety of devices using the broadband link, and clocking is performed with a combination of bit clocks and frame clocks that are adjustable to accommodate needs of disparate types of data, including data for an xDSL communications path, xDSL samples from different analog codecs for xDSL modems, and ATM cells for an ATM interfaces. The I/O circuits include multiple bus interfaces to make them more flexibly integrated into a variety of application environments.

Abstract: A new processing sequence is provided for the process of creating salicided layers of CoSix. A conventional gate electrode is formed up to the point where the process of salicidation has to be performed. At that time a layer of cobalt is deposited over the surface of the gate electrode, a first anneal is applied to the deposited layer of cobalt. The layer of cobalt is then selectively etched to formed the contact surfaces of the gate electrode after which, significantly and as a major deviation from previous methods of creating a salicided layer of CoSix, silicon is implanted into the surface of the created layer of CoSix. This silicon implant relieves a silicon deficiency into the first annealed layer of CoSix, this silicon deficiency has experimentally been determined as being the essential cause for the occurrence of Co—Si agglomeration after a second thermal anneal. After the silicon implantation has been completed, a second thermal anneal is applied to the created layer of CoSix.

Abstract: A system that can be dynamically configured to achieve an optimal routing path for an end-to-end data link connection is disclosed. An optimal data path can be determined by a digital subscriber loop (DSL) user based on particular bandwidth requirements, data rate cost constraints, and/or data delay requirements. The data path can be set up to include one or more data routes, including the regular digital public switching telephone network (PSN), a wide area networks (WAN), or virtual permanent circuit links via digital cross-connects (DCS).

Abstract: A method is taught for removing a silicon oxynitride ARC from over a polysilicon gate after the gate is patterned. The ARC is removed by wet etching without damaging or undercutting the polysilicon gate. This is accomplished by protecting the lateral sides of a polysilicon gate with a thin silicon oxide layer prior to the performing the wet etch. The method is primarily directed towards removal of a silicon oxynitride ARC layer from the upper surface of the polysilicon gate electrode in a salicide process, although a silicon nitride layer may also be removed by the same method. The protective silicon oxide is formed by rapid thermal oxidation in O2 or by plasma oxidation in O2 and H2O. After oxidation, the ARC is removed with hot H3PO4. The protective silicon oxide protects the lateral surfaces of the polysilicon gate from attack by the acid. Following implantation of LDD regions, a conformal sidewall layer is deposited and the sidewalls formed in the conventional manner.

Abstract: The invention relates to a fast alignment telescopic sight for use in connection with firearms to improve sighting accuracy. It comprises a tube, an optical sighting system, and an alignment unit. An alignment mark is provided in the target image plane of the optical sighting system, and is coupled to the tube through an adjustable connection unit. The adjustable connection unit comprises a base coupled to the tube, an adjustable positioning support mounted in the base, and a rotation pin passing through and secured to the adjustable positioning support. The alignment mark is secured to the front end of the rotation pin. The invention can be used for adjusting the alignment mark in arbitrary directions to ensure the alignment mark to be exactly located in the target image plane and at the center of the field of view against various manufacturing errors. The invention features simple construction, reliable performance and low manufacturing cost.

Abstract: An analog front end (AFE) circuit used in a high-speed communications system is presented that includes multiple stages each including a bandpass filter, base band modulator, low pass filter and Sigma-Delta modulator. Each stage processes a fractional portion of the total frequency of a wide bandwidth analog signal. The number of such AFE stages is configurable in parallel to process the entire bandwidth of the received signal. The AFEs can be incorporated in a single integrated circuit or similar suitable manner so as to be modular, and easily replaceable/upgradeable. To achieve minimum quantization noise and reduce manufacturing costs, the Sigma-Delta modulators in each AFE are made to have identical characteristics. Because the wideband signal is broken down into smaller frequency portions, the sampling rate, and thus the complexity and cost associated with the AFEs, is reduced significantly.

Abstract: A method of forming a misalignment immune antifuse is presented comprised of the following steps. A partially processed semiconductor wafer is provided, containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where the conducting region is surrounded by a dielectric layer which reaches the wafer surface. A blanket layer of amorphous silicon is deposited followed by deposition of a thin blanket layer of TiN and these layers are etched down to the dielectric surface except for that above the conducting region and some of the surrounding dielectric. A thin native oxide is formed over the exposed surface of the amorphous silicon. This is followed by deposition of a thicker TIN layer and of a metallization layer, which are patterned and etched so that contact is made to the lower layers. The oxidation step is repeated so as to oxidize any amorphous silicon surface that may have been inadvertently exposed in the last etching step.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A device or interface driver is provided for permitting an operating system to utilize, configure and control a software modem having forward compatible and expandable functionality. In a preferred embodiment, the operating system is a Windows based system running on a host processing system such as a personal computer, and the modem is compatible with standards promulgated for ADSL. Conventional voice band modem control commands are also supported, so that the present invention for ADSL based modems is nevertheless compatible with existing modem applications programs. The new driver manages control information for configuring the bandwidth to be used in a data link established through a channel with an upstream transciever during an initialization process, and serves as a data pump for the software modem. The control information may be self-determined by a user of the host processing system 398, or alternatively, automatically sensed, configured and monitored by such processing system.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.