Patents by Inventor Kang Rim Choi
Kang Rim Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11387162Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.Type: GrantFiled: June 9, 2020Date of Patent: July 12, 2022Assignee: Littelfuse, Inc.Inventors: Gi-Young Jeun, Kang Rim Choi
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Publication number: 20200303281Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.Type: ApplicationFiled: June 9, 2020Publication date: September 24, 2020Applicant: IXYS, LLCInventors: Gi-Young Jeun, Kang Rim Choi
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Patent number: 10763201Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.Type: GrantFiled: November 23, 2017Date of Patent: September 1, 2020Assignee: Littelfuse, Inc.Inventors: Nathan Zommer, Kang Rim Choi
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Patent number: 10720376Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.Type: GrantFiled: November 2, 2018Date of Patent: July 21, 2020Assignee: Littelfuse, Inc.Inventors: Gi-Young Jeun, Kang Rim Choi
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Publication number: 20190088571Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.Type: ApplicationFiled: November 2, 2018Publication date: March 21, 2019Applicant: IXYS, LLCInventors: Gi-Young Jeun, Kang Rim Choi
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Publication number: 20180096918Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.Type: ApplicationFiled: November 23, 2017Publication date: April 5, 2018Inventors: Nathan Zommer, Kang Rim Choi
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Patent number: 9842795Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.Type: GrantFiled: July 1, 2014Date of Patent: December 12, 2017Assignee: IXYS CorporationInventors: Nathan Zommer, Kang Rim Choi
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Publication number: 20170178998Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.Type: ApplicationFiled: March 7, 2017Publication date: June 22, 2017Inventors: Gi-Young Jeun, Kang Rim Choi
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Patent number: 9177888Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.Type: GrantFiled: December 1, 2014Date of Patent: November 3, 2015Assignee: IXYS CorporationInventors: Thomas Spann, Holger Ostmann, Kang Rim Choi
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Publication number: 20150087113Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.Type: ApplicationFiled: December 1, 2014Publication date: March 26, 2015Inventors: Thomas Spann, Holger Ostmann, Kang Rim Choi
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Patent number: 8901723Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.Type: GrantFiled: April 30, 2013Date of Patent: December 2, 2014Assignee: IXYS CorporationInventors: Thomas Spann, Holger Ostmann, Kang Rim Choi
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Publication number: 20140312477Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Inventors: Nathan Zommer, Kang Rim Choi
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Patent number: 8796837Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.Type: GrantFiled: September 17, 2009Date of Patent: August 5, 2014Assignee: IXYS CorporationInventors: Nathan Zommer, Kang Rim Choi
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Publication number: 20130252381Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.Type: ApplicationFiled: April 30, 2013Publication date: September 26, 2013Applicant: IXYS CorporationInventors: Thomas Spann, Holger Ostmann, Kang Rim Choi
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Publication number: 20130175704Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: IXYS CorporationInventors: Gi-Young Jeun, Kang Rim Choi
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Patent number: 8455987Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.Type: GrantFiled: April 30, 2010Date of Patent: June 4, 2013Assignee: IXYS CorporationInventors: Thomas Spann, Holger Ostmann, Kang Rim Choi
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Publication number: 20100224982Abstract: A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions.Type: ApplicationFiled: September 17, 2009Publication date: September 9, 2010Applicant: IXYS CorporationInventors: Nathan Zommer, Kang Rim Choi
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Patent number: 7459659Abstract: A heating circuit for heating a conductive bowl includes a voltage source; a first heating coil provided between first and second nodes and being configured to heat the conductive bowl; a second heating coil provided between the second node and a third node and being configured to heat the conductive bowl; first capacitor and first switch provided in parallel between the first node and a fourth node; and second capacitor and second switch provided in parallel between the third node and the fourth node. The first and second heating coils define a circle-like shape having a center. The first and second heating coils are configured to be aligned to each other if one of the first and second heating coils is moved with respect to a line extending through the center of the circle-like shape.Type: GrantFiled: April 20, 2007Date of Patent: December 2, 2008Assignee: IXYS CorporationInventors: Kyoung Wook Seok, Kang Rim Choi
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Publication number: 20070246458Abstract: A heating circuit for heating a conductive bowl includes a voltage source; a first heating coil provided between first and second nodes and being configured to heat the conductive bowl; a second heating coil provided between the second node and a third node and being configured to heat the conductive bowl; first capacitor and first switch provided in parallel between the first node and a fourth node; and second capacitor and second switch provided in parallel between the third node and the fourth node. The first and second heating coils define a circle-like shape having a center. The first and second heating coils are configured to be aligned to each other if one of the first and second heating coils is moved with respect to a line extending through the center of the circle-like shape.Type: ApplicationFiled: April 20, 2007Publication date: October 25, 2007Applicant: IXYS CorporationInventors: Kyoung Wook SEOK, Kang Rim Choi
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Patent number: 7005734Abstract: A power device includes a semiconductor die having an upper surface and a lower surface. One or more terminals are coupled to the die. A first substrate is bonded to the upper surface of the die. The first substrate is configured to provide a first heat dissipation path. A second substrate is bonded to the lower surface of the die. The second substrate is configured to provide a second heat dissipation path.Type: GrantFiled: May 5, 2003Date of Patent: February 28, 2006Assignee: IXYS CorporationInventors: Kang Rim Choi, Nathan Zommer