Patents by Inventor Kang Rim Choi

Kang Rim Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040222515
    Abstract: A power device includes a semiconductor die having an upper surface and a lower surface. One or more terminals are coupled to the die. A first substrate is bonded to the upper surface of the die. The first substrate is configured to provide a first heat dissipation path. A second substrate is bonded to the lower surface of the die. The second substrate is configured to provide a second heat dissipation path.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 11, 2004
    Applicant: IXYS Corporation
    Inventors: Kang Rim Choi, Nathan Zommer
  • Patent number: 6731002
    Abstract: A radio frequency power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses and protects the semiconductor die. A plurality of leads extend outwardly from the plastic package. The leads have blade-like shapes.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: May 4, 2004
    Assignee: IXYS Corporation
    Inventor: Kang Rim Choi
  • Patent number: 6727585
    Abstract: A power device compatible with an SOT 227 package standard. The device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The first conductive layer has been patterned to provide at least first and second conductive blocks. A semiconductor die is bonded to the first block of the first conductive layer of the substrate. A terminal lead is coupled to the second block of the first conductive layer of the substrate.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: April 27, 2004
    Assignee: Ixys Corporation
    Inventor: Kang Rim Choi
  • Patent number: 6710463
    Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: March 23, 2004
    Assignee: IXYS Corporation
    Inventor: Kang Rim Choi
  • Publication number: 20030186483
    Abstract: A packaged power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The substrate has a lower surface. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses the die and has a lower surface. A curved backside includes the lower surfaces of the plastic package and substrate.
    Type: Application
    Filed: March 19, 2003
    Publication date: October 2, 2003
    Applicant: IXYS Corporation
    Inventor: Kang Rim Choi
  • Patent number: 6583505
    Abstract: A packaged power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The substrate has a lower surface. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses the die and has a lower surface. A curved backside includes the lower surfaces of the plastic package and substrate.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: June 24, 2003
    Assignee: Ixys Corporation
    Inventor: Kang Rim Choi
  • Patent number: 6534343
    Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: March 18, 2003
    Assignee: Ixys Corporation
    Inventor: Kang Rim Choi
  • Publication number: 20020171134
    Abstract: A packaged power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The substrate has a lower surface. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses the die and has a lower surface. A curved backside includes the lower surfaces of the plastic package and substrate.
    Type: Application
    Filed: March 13, 2002
    Publication date: November 21, 2002
    Applicant: IXYS Corporation
    Inventor: Kang Rim Choi
  • Publication number: 20020163074
    Abstract: A power device compatible with an SOT 227 package standard. The device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The first conductive layer has been patterned to provide at least first and second conductive blocks. A semiconductor die is bonded to the first block of the first conductive layer of the substrate. A terminal lead is coupled to the second block of the first conductive layer of the substrate.
    Type: Application
    Filed: March 13, 2002
    Publication date: November 7, 2002
    Applicant: IXYS Corporation
    Inventor: Kang Rim Choi
  • Publication number: 20020163070
    Abstract: A radio frequency power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses and protects the semiconductor die. A plurality of leads extend outwardly from the plastic package. The leads have blade-like shapes.
    Type: Application
    Filed: November 13, 2001
    Publication date: November 7, 2002
    Applicant: IXYS Corporation
    Inventor: Kang Rim Choi
  • Patent number: 6404065
    Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: June 11, 2002
    Assignee: I-XYS Corporation
    Inventor: Kang Rim Choi
  • Publication number: 20020017714
    Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.
    Type: Application
    Filed: September 5, 2001
    Publication date: February 14, 2002
    Inventor: Kang Rim Choi
  • Publication number: 20010018235
    Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.
    Type: Application
    Filed: May 8, 2001
    Publication date: August 30, 2001
    Inventor: Kang Rim Choi