Abstract: A transcutaneous multimodal delivery device for drug delivery and the methods of making and using the same are provided.

Abstract: Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage.

Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.

Abstract: Among other things, one or more systems and techniques for defining one or more implant regions or for doping a semiconductor arrangement are provided. A first implant region is defined based upon a first implant mask overlaying a first active region of a semiconductor arrangement. A second implant region is defined based upon the first implant mask and a second implant mask overlaying a second active region of the semiconductor arrangement. A third implant region is defined based upon the second implant mask overlaying a third active region of the semiconductor arrangement. One or more doping processes are performed through the first implant mask and the second implant mask to dope the semiconductor arrangement. Because the first implant mask and the second implant mask overlap the second active region, doping area coverage is improved thus mitigating undesirable voltage threshold variations otherwise resulting from inadequate doping area coverage.

Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner.

Abstract: A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask.

Abstract: A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.

Abstract: The present invention provides a fibromodulin (FMOD) reprogrammed (FReP) cell and a method of making therefor, a culture medium therefor, and a supernatant thereof, and methods of making and using these.

Abstract: The present invention provides a method and system for producing a NELL protein. The method and system comprise a CELL encoding a NELL protein or peptide and a non-insect secretory signal peptide.

Abstract: A method of fabricating a semiconductor device includes forming a first metal gate electrode over a substrate, forming a second metal gate electrode over the substrate, removing at least a part of the first metal gate electrode to form a first opening, and filling the first opening with a non-conductive material.

Abstract: Implant-associated bacterial infections are one of the most serious complications in orthopedic surgery. Treatment of these infections often requires multiple operations, device removal, long-term systemic antibiotics, and extended rehabilitation, and is frequently ineffective, leading to worse clinical outcomes and increased financial costs. Silver nanoparticle/poly(DL-lactic-co-glycolic acid) (PLGA)-coated stainless steel alloy (SNPSA) was evaluated as a potential antimicrobial implant material. It was found that SNPSA exhibited strong antibacterial activity in vitro and ex vivo, and promoted MC3T3-E1 pre-osteoblasts proliferation and maturation in vitro. Furthermore, SNPSA implants induced osteogenesis while suppressing bacterial survival in contaminated rat femoral canals. The results indicate that SNPSA has simultaneous antimicrobial and osteoinductive properties that make it a promising therapeutic material in orthopedic surgery.

Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.

Abstract: A target integrated circuit layout having a plurality of design rules having minimum rules and standard rules used in the target integrated circuit layout is provided. First and second design rule checks are performed, where respective first and second sets of violations of the plurality of design rules and each design rule associated with the first and second sets of violations are recorded. An analysis is performed on the first and second sets of violations, each design rule associated with the first and second sets of violations, and a frequency of usage of each of the plurality of design rules, and a rule usage rate is determined having a number of minimum rules used overall and a number of overall violations of the design rules. An interactive rule database is formed having statistics associated with the rule usage rate for subsequent implementation in an integrated circuit.

Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.

Abstract: A semiconductor device includes a non-conductive gate feature over a substrate and a spacer adjoining each sidewall of the non-conductive gate feature.

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract: The present invention discloses methods and compositions for treating or ameliorating a condition associated with increased or decreased myofibroblast activities and use thereof

Abstract: A method of fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. In at least one embodiment, a non-conductive material is used for forming the dummy gate feature to replace a sacrificial gate electrode.

Abstract: Embodiments of the present invention provide a population of purified perivascular stem cells (PSC) or induced pluripotent stem cells (iPS) and a supernatant of stem cell free from the stem cell, a composition comprising any of these, and a method of using and making them.

Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.