Patents by Inventor Kang Ting

Kang Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060228392
    Abstract: This invention pertains to the discovery that the human NELL-1 gene induces or upregulates bone mineralization. The NELL-1 gene or gene product thus provides a convenient target for screening for modulators of bone mineralization. In addition, NELL-1 can be used to facilitate repair of bone fractures and/or to generally increase bone density.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 12, 2006
    Inventor: Kang Ting
  • Publication number: 20060146636
    Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.
    Type: Application
    Filed: January 26, 2006
    Publication date: July 6, 2006
    Inventors: Jen-Shou Hsu, Tah-Kang Ting, Ming-Hung Wang, Bor-Doou Rong
  • Publication number: 20060119417
    Abstract: A method and apparatus are provided for improving the efficiency in charge pump systems for low power applications. This first embodiment provides a method and apparatus which defines a charge pump output voltage high target which turns off a charge pump enable signal and a charge pump outlet voltage low target which turns on a charge pump enable signal. A second embodiment defines a protection time where the charge pumping continues until a predefined phase is completed and the leakage paths are disabled. A third embodiment defines a phase memory block, which continues or remembers the phase until the next request for charge pumping. This prevents the circuitry from entering a window where charge leakage, which diminishes charge pumping efficiency, could occur.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 8, 2006
    Inventors: Jenshou Hsu, Tah-Kang Ting
  • Patent number: 7052856
    Abstract: This invention pertains to the discovery that the human NELL-1 gene induces or upregulates bone mineralization. The NELL-1 gene or gene product thus provides a convenient target for screening for modulators of bone mineralization. In addition, NELL-1 can be used to facilitate repair of bone fractures and/or to generally increase bone density.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: May 30, 2006
    Assignee: The Regents of the University of California
    Inventor: Kang Ting
  • Publication number: 20060111313
    Abstract: This invention pertains to the discovery that the human NELL-1 gene induces or upregulates bone mineralization. The HELL-1 gene or gene product thus provides a convenient target for screening for modulators of bone mineralization. In addition, HELL-1 can be used to facilitate repair of bone fractures and/or to generally increase bone density.
    Type: Application
    Filed: September 15, 2003
    Publication date: May 25, 2006
    Inventor: Kang Ting
  • Publication number: 20050270880
    Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.
    Type: Application
    Filed: June 4, 2004
    Publication date: December 8, 2005
    Inventors: Jen-Shoe Hsu, Tah-Kang Ting, Ming-Hung Wang, Bor-Doou Rong
  • Patent number: 6800869
    Abstract: A monitoring apparatus for a tape automated bonding process, which is used to attach a plurality of flexible substrates constructed in the form of a tape to an edge of a rigid substrate, the monitoring apparatus comprises a sensor for sensing the variation of an optical signal and being moved along the edge of the rigid substrate so as to monitor the quantity of the flexible substrates according to the number of the variation of the optical signal.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: October 5, 2004
    Assignee: Hannstar Display Corp.
    Inventor: Kang Ting Liu
  • Patent number: 6795156
    Abstract: An orientation inspector for LCD cell is utilized to inspect the LCD cell. The LCD cell includes two transparent substrates wherein the first transparent substrate is slightly bigger than the second transparent substrate and a step is formed on the first transparent substrate along the two side edges thereof. The orientation inspector for LCD cell comprises a main body connected to a hoister which can lower the main body to a predetermined position to stop the step at side edge of the LCD cell; a sensor disposed in the main body for detecting the step at side edge of the LCD cell below the main body, wherein when the body stops the step at side edge of the LCD cell and the sensor detects the step on the first transparent substrate, the sensor will confirm that the LCD cell is at correct orientation, and when the main body stops the side edge of the LCD cell and the sensor can not detect the step on the first transparent substrate, the sensor will confirm that the LCD cell is not at correct orientation.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: September 21, 2004
    Assignee: Hannstar Display Corp.
    Inventor: Kang Ting Liu
  • Publication number: 20030158602
    Abstract: This invention pertains to the discovery that the human NELL-1 gene induces or upregulates bone mineralization. The NELL-1 gene or gene product thus provides a convenient target for screening for modulators of bone mineralization. In addition, NELL-1 can be used to facilitate repair of bone fractures and/or to generally increase bone density.
    Type: Application
    Filed: October 5, 1999
    Publication date: August 21, 2003
    Inventor: KANG TING
  • Publication number: 20020140565
    Abstract: A monitoring apparatus for a tape automated bonding process, which is used to attach a plurality of flexible substrates constructed in the form of a tape to an edge of a rigid substrate, the monitoring apparatus comprises a sensor for sensing the variation of an optical signal and being moved along the edge of the rigid substrate so as to monitor the quantity of the flexible substrates according to the number of the variation of the optical signal.
    Type: Application
    Filed: August 30, 2001
    Publication date: October 3, 2002
    Applicant: HannStar Display Corp.
    Inventor: Kang Ting Liu
  • Publication number: 20020134814
    Abstract: A stroke and pressure adjusting device is used for the soldering process of a soldering machine which has a driving device for driving a soldering device of the soldering machine to solder, and the driving device has a driving shaft on which the stroke and pressure adjusting device is attached. The stroke and pressure adjusting device comprises a thread sleeve mounted on the driving shaft of the driving device, a slider mounted on the thread sleeve, and a spring mounted between the slider and the driving device, wherein the distance between the thread sleeve and the driving device is adjustable so as to adjust the stroke of the driving device, the distance between the slider and the driving device is adjustable and the distance between the slider and the driving device is adjustable so as to adjust the elastic force generated by the spring, thereby adjusting the operating pressure of the driving device.
    Type: Application
    Filed: August 22, 2001
    Publication date: September 26, 2002
    Applicant: HANNSTAR DISPLAY CORP.
    Inventor: Kang Ting Liu
  • Patent number: 6454155
    Abstract: A stroke and pressure adjusting device is used for the soldering process of a soldering machine which has a driving device for driving a soldering device of the soldering machine to solder, and the driving device has a driving shaft on which the stroke and pressure adjusting device is attached. The stroke and pressure adjusting device comprises a thread sleeve mounted on the driving shaft of the driving device, a slider mounted on the thread sleeve, and a spring mounted between the slider and the driving device, wherein the distance between the thread sleeve and the driving device is adjustable so as to adjust the stroke of the driving device, the distance between the slider and the driving device is adjustable and the distance between the slider and the driving device is adjustable so as to adjust the elastic force generated by the spring, thereby adjusting the operating pressure of the driving device.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: September 24, 2002
    Assignee: Hannstar Display Corp.
    Inventor: Kang Ting Liu
  • Publication number: 20020060755
    Abstract: An orientation inspector for LCD cell is utilized to inspect the LCD cell. The LCD cell includes two transparent substrates wherein the first transparent substrate is slightly bigger than the second transparent substrate and a step is formed on the first transparent substrate along the two side edges thereof. The orientation inspector for LCD cell comprises a main body connected to a hoister which can lower the main body to a predetermined position to stop the step at side edge of the LCD cell; a sensor disposed in the main body for detecting the step at side edge of the LCD cell below the main body, wherein when the body stops the step at side edge of the LCD cell and the sensor detects the step on the first transparent substrate, the sensor will confirm that the LCD cell is at correct orientation, and when the main body stops the side edge of the LCD cell and the sensor can not detect the step on the first transparent substrate, the sensor will confirm that the LCD cell is not at correct orientation.
    Type: Application
    Filed: September 7, 2001
    Publication date: May 23, 2002
    Applicant: HannStar Display Corp.
    Inventor: Kang Ting Liu
  • Publication number: 20020060896
    Abstract: A static electricity discharging loader for sheet materials is utilized discharging the static electricity on stacked sheet materials and the sheet materials are stacked on the static electricity discharging loader and the loader comprises a container to contain the sheet materials, a static electricity discharging device with a static electricity discharging brush and when the sheet materials is taken out the container, the sheet materials will contact the static electricity discharging brush and then remove the static electricity on it so that the sheet materials are taken out from the container smoothly.
    Type: Application
    Filed: September 6, 2001
    Publication date: May 23, 2002
    Applicant: HannStar Display Corp.
    Inventor: Kang Ting Liu
  • Patent number: 6169314
    Abstract: This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: January 2, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shyh-Chyi Wong, Pin-Nan Tseng, Jyh-Kang Ting
  • Patent number: 5952698
    Abstract: This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: September 14, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Chyi Wong, Pin-Nan Tseng, Jyh-Kang Ting
  • Patent number: 5838032
    Abstract: Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects during etching, the areas of the electrodes of the capacitors located along the edges of the array have tended to be slightly less than the areas of electrodes located completely inside the array. The present invention solves this problem by providing additional electrodes located along the periphery of the array, spaced the same distance away from the array edge as the spacing between electrodes inside the array.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: November 17, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventor: Jyh-Kang Ting
  • Patent number: 5804488
    Abstract: A method for making a polycide-to-polysilicon capacitor having an improved breakdown voltage is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. An oxide layer is formed over the silicide layer, and the silicide layer is then annealed. A second layer of doped polysilicon is formed over the oxide layer. The second layer of doped polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: September 8, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi Shih, Shun-Liang Hsu, Jyh-Kang Ting
  • Patent number: 5635421
    Abstract: Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects during etching, the areas of the electrodes of the capacitors located along the edges of the array have tended to be slightly less than the areas of electrodes located completely inside the array. The present invention solves this problem by providing additional electrodes located along the periphery of the array, spaced the same distance away from the array edge as the spacing between electrodes inside the array.
    Type: Grant
    Filed: June 15, 1995
    Date of Patent: June 3, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jyh-Kang Ting
  • Patent number: D488143
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: April 6, 2004
    Assignee: Quanta Computer Inc.
    Inventors: Chih-Kang Ting, Chun-Chieh Peng, Gwo-Chyuan Chen