Abstract: The invention provides a method for gain error estimation for an analog-to-digital converter. In one embodiment, the analog-to-digital converter comprises a plurality of stages. First, a series of correction numbers applied to a target stage selected from the stages are correlated with a series of first values calculated according to digital output values of the stages to generate a series of gain error estimates. Every first number of the series of gain error estimates is then averaged to obtain a series of second values. A second number of the series of second values is then averaged to obtain a gain error of the target stage.

Abstract: The invention provides an analog-to-digital converter (ADC). The ADC comprises a plurality of stages connected in series, a gain error correction module, and a look-ahead module. Each of the stages derives a stage output value from a stage input signal and generates a stage output signal as the stage input signal of a subsequent stage, wherein one of the stages is selected as a target stage for estimating a gain value thereof. The gain error correction module delivers a correction number to the target stage to affect the stage output signal of the target stage and the stage output values of subsequent stages of the target stage, receives at least one auxiliary output value from a look-ahead module dedicated to the target stage, and derives an error estimate of the gain value of the target stage from the stage output values and the auxiliary output value.

Abstract: A digital television chip having a reduced layout size is disclosed, comprising a multiplexer, and first and second converting units. The multiplexer, according to a control signal, outputs one of S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs a CVBS Line-in Video signal to one of the first and second converting units, for reducing the size of the chip. The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing.