Patents by Inventor Kang Yong Kim

Kang Yong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240070096
    Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Yang Lu, Creston M. Dupree, Kang-Yong Kim
  • Publication number: 20240070102
    Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Yang Lu, Creston M. Dupree, Smruti Subhash Jhaveri, Hyun Yoo Lee, John Christopher Sancon, Kang-Yong Kim, Francesco Douglas Verna-Ketel
  • Publication number: 20240066565
    Abstract: A self-cleaning device comprises at least one first electrode disposed on a solid material layer, a first dielectric layer disposed on the first electrode, a hydrophobic layer disposed on the first dielectric layer, and at least one mechanical oscillation unit. Electrical oscillation for oscillating a droplet in a horizontal direction is generated by applying a first electric signal to the first electrode, thereby merging droplets formed on the hydrophobic layer, the mechanical oscillation unit moves the merged droplets in a specific direction or atomizes the merged droplets to remove the merged droplets by generating mechanical oscillation for oscillating the droplet in a vertical direction, and each of the droplets has a volume smaller than 3 ?l, and new droplet having a volume more than 3 ?l is generated by the merging.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 29, 2024
    Inventors: Sang Kug CHUNG, Kang Yong LEE, Jeong Min LEE, Dae Young LEE, Dae Geun KIM
  • Publication number: 20240071437
    Abstract: Described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. A nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. The nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. Die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. The disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. Thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Yang Lu, Kang-Yong Kim
  • Publication number: 20240070101
    Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Francesco Douglas Verna-Ketel, Hyun Yoo Lee, Smruti Subhash Jhaveri, John Christopher Sancon, Yang Lu, Kang-Yong Kim
  • Publication number: 20240070093
    Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim, Jason McBride Brown, Venkatraghavan Bringivijayaraghavan, Vijayakrishna J. Vankayala
  • Publication number: 20240071461
    Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: John Christopher Sancon, Kang-Yong Kim, Yang Lu, Hyun Yoo Lee
  • Publication number: 20240071464
    Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Erik T. Barmon, Yang Lu, Nathaniel J. Meier, Kang-Yong Kim
  • Patent number: 11907544
    Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 11908544
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: February 20, 2024
    Inventor: Kang-Yong Kim
  • Patent number: 11894099
    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Hyun Yoo Lee, Timothy M. Hollis, Dong Soon Lim
  • Publication number: 20240029771
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Application
    Filed: May 2, 2023
    Publication date: January 25, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Kang-Yong Kim
  • Publication number: 20240029770
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Application
    Filed: May 1, 2023
    Publication date: January 25, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Kang-Yong Kim
  • Publication number: 20240029778
    Abstract: In various examples, refreshing a bank can include receiving a refresh command, wherein the refresh command comprises selector bits and receiving mode register bits from the mode registers. Refreshing a bank can also include refreshing a number of banks from the plurality of banks utilizing the mode register bits and the selector bits.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Inventors: Yang Lu, Kang-Yong Kim
  • Patent number: 11869626
    Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Hyunyoo Lee
  • Patent number: 11868638
    Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sourabh Dhir, Kang-Yong Kim
  • Patent number: 11868650
    Abstract: Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first emphasized characteristic and a second memory circuit having a second emphasized characteristic. The first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 11842791
    Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: December 12, 2023
    Inventor: Kang-Yong Kim
  • Publication number: 20230393748
    Abstract: Systems, apparatuses, and methods related to memory system refresh management are described herein. In an example, a refresh operation can be performed on a set of memory cells in a memory device. The memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The refresh operation can include receiving a mode register write command. The refresh operation can include writing mode register data associated with the mode register write command. The refresh operation can be performed on the set of memory cells at an address location indicated by the written mode register data.
    Type: Application
    Filed: October 14, 2022
    Publication date: December 7, 2023
    Inventors: Yang Lu, Kang-Yong Kim
  • Patent number: 11830575
    Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: November 28, 2023
    Inventor: Kang-Yong Kim